JPS63197118A - Phase locked loop - Google Patents

Abstract

PURPOSE:To reduce the lock time by outputting a 2nd signal having an oscillation frequency close to a 1st signal immediately from the 2nd signal when the frequency of the 1st signal inputted by the frequency detection means is detected. CONSTITUTION:LPFs (low pass filters) l1, l2...lN being arithmetic means holding an output level corresponding based on the 1st signal frequency detected by a frequency detection circuit 11 are selected. Thus, an input level sufficiently to output an oscillation frequency nearly equal to the 1st signal frequency is obtained momentarily to a voltage controlled oscillator 12. Then the phase difference between the 1st and 2nd signals having the set oscillating frequency is detected by a phase comparator 13 and an output level corresponding to the phase difference is calculated by the LPF 14 and the result is supplied to the voltage controlled oscillator 12. Thus, the phase is corrected and the phase locked loop (PLL) is locked. Thus, the lock time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a 7-ray locked loop (PLL:P
hase L asked Loop) circuit.

Prior Art FIG. 3 is a block diagram showing the electrical configuration of a typical prior art PLL circuit 1. A PLL circuit 1 includes a voltage controlled oscillator 2 whose oscillation frequency changes depending on the magnitude of the voltage level supplied from the outside, and a frequency of an input signal (2) input to the PLL circuit 1 and an output signal C of the voltage controlled oscillator 2.
The voltage level VF corresponding to the difference is compared with the frequency of
, and a phase comparator 4 that outputs a voltage level P corresponding to the phase difference between the input signal I and the output signal C of the voltage controlled oscillator 2.
The above two voltage levels VF and VP are I! The signal is applied to the voltage controlled oscillator 2 via an LPF (low pass filter) 5 filtered by a branch circuit or the like.

FIG. 4 is a timing chart for explaining the operation of the PLL circuit 1. The operation of the PLL circuit 1 will now be described assuming that the frequency ft of the input signal I changes to the frequency "b" at time to as shown in FIG.

Until the time to, the input signal ■ with the frequency "a" is constantly inputted with the period Ta, so the period of the output signal C of the voltage controlled oscillator 2 is set equal to the period Ta of the input signal generator (see FIG. 2)), because the output level of the LPF 5 input to the voltage controlled oscillator 2 is such that the oscillation frequency of the voltage controlled oscillator 2 is equal to the frequency rm of the input signal ■, as shown in (4) of the same figure. This is because the voltage level Va is maintained.

Then, when the period Ta of the input signal I changes to the period Tb from time to, the frequency comparator 3 outputs the two signals 1. The voltage level VF corresponding to the frequency difference of C
is given to the LPF 5 (see (3) in the same figure), charging starts within the LPFS, and the LPF5 output level increases sequentially as shown in (4) in the same figure.Therefore, voltage controlled oscillation is started. The oscillation frequency of n2 increases. Therefore, when the period of the output signal C of the voltage controlled oscillator 2 approaches the period Tb of the input signal I, the frequency comparator 3 becomes high impedance (time t2), and the output level of the LPF 5 is held constant. In addition, the DC voltage VF from the frequency comparator 3
During the charging period t during which the phase comparator 4
is high impedance.

Therefore, at time t3, the phase comparator 4 outputs a DC voltage VP corresponding to the phase difference between the input signal ■ and the output signal C.
I is output, thereby increasing the oscillation frequency of the voltage controlled oscillator 2. In this way, the phase comparator 4 outputs a DC voltage corresponding to the phase difference in each cycle until the phase difference between the input signal ■ and the output signal C becomes zero. In this way, at time t4, the output signal C of the voltage controlled oscillator 2 is synchronized with the input signal ■, and the PLL circuit enters a locked state.

Problems to be Solved by the Invention In this way, when the PLL circuit 1 receives an input signal I having a frequency different from the output signal C from the voltage controlled oscillator 2, it first adjusts the frequency and then corrects the phase. . However, to adjust the frequency, the LP
It is necessary to charge the DC voltage VF from the frequency comparator 3 within the FS, and the charging period t until charging is completed takes a long time. Therefore, responsiveness was degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked loop circuit that solves the above-mentioned problems and reduces locking time.

Means for Solving the Problems The present invention provides: frequency detection means for detecting the frequency of an input first signal; oscillation means for outputting a second signal having an oscillation frequency corresponding to the input voltage level; and tttJ1 signal. phase difference detection means for detecting a phase difference between the signal and the second signal and outputting a voltage level corresponding to this phase difference; A plurality of calculation means are provided in parallel between each other and calculate the output level from the phase difference detection means and each hold the output level, and each calculation means is connected in parallel and the frequency detection means detects the 1 corresponding to the frequency of the signal
The first calculation means is selected and connected to the phase difference detection means.
A phase-locked loop circuit characterized in that it includes a switching means and a second switching means for connecting the selected calculation means and the oscillation means.

Function: In the 7-way idle lock circuit according to the present invention,
The first and second switching means are controlled in accordance with the frequency of the first signal detected by the frequency detection means. The first switching means connects the arithmetic means in which an output level corresponding to the frequency of the first signal is maintained and the phase difference detection means, and the second switching means connects the selected arithmetic means and the oscillation means. Connecting. As a result, the output level held by the selected calculation means is applied to the oscillation means, and the oscillation means outputs a second signal having an oscillation frequency corresponding to the output level.

MS detected by the frequency detection means in this way
Based on the 1S2O frequency, the calculation means that maintains the corresponding output level is selected, so that the oscillation means receives an input level sufficient to instantaneously output an oscillation frequency approximately equal to the frequency of the first signal. .

Next, the phase difference between the #22 signal having the oscillation frequency set as described above and the first signal is detected by the phase difference detection means, and the output level corresponding to this phase difference is calculated by the calculation means. given to the oscillation means. This corrects the phase and locks the phase-locked loop circuit.

Embodiment FIG. 1 is a block diagram showing the electrical configuration of a PLL circuit 10 which is an embodiment of the present invention. The PLL circuit 10 is
a frequency detection circuit 11 that detects the frequency of the input signal 11;
A voltage controlled oscillator 12 that outputs an output signal C1 having an oscillation frequency corresponding to an input voltage level, the output signal C
1 and the input signal 11, and a phase comparison 'n13 which is a phase difference detection means that detects the phase difference between the input signal 11 and the input signal 11 and outputs a voltage level corresponding to the detected phase difference, and an LPF (low pass filter) 71tJ! which is N calculation means. 2=..., J! N (hereinafter collectively referred to as LPF14) and these LPF1
It is composed of analog switches SWI and SW2, which are first and second switching means for selectively controlling the switch 4.

N LPFs! 1,72. ...t, i'N are connected in parallel to two analog switches SWI and SW2, respectively, and the output of the phase comparator 13 is connected to the analog switch SW
1, while the output of analog switch SW2 is provided to voltage controlled oscillator 12.

In addition, the two analog switches SWI and SW2 are controlled by the control signal outputted from the frequency detection circuit 11.
PF, /1. /2. ..., the desired L from N
PF can be selectively controlled.

The PLL circuit 10 is configured for the purpose of synchronizing and locking the output signal C1 of the voltage controlled oscillator 12 with the input signal 1 inputted to the PLL circuit 10.

That is, the voltage level corresponding to the frequency of the input signal 11 detected by the frequency detection means 11 is given to the voltage controlled oscillator @12, and as a result, the voltage controlled oscillator 12 generates an oscillation frequency close to the frequency of the input signal 1. The output signal C1 having the output signal C1 is applied to the phase comparator 13, and a voltage level corresponding to the phase difference between the two signals is applied to the voltage controlled oscillator 12. Roughly speaking, the two signals are synchronized by the above-described operation. This will be explained in detail below.

N LPFs, /1,72. ..., 7N is PL
When the L circuit 10 is powered on, it is charged to a different predetermined voltage level by a power supply means (not shown), and thereafter this voltage level is maintained unless the LPF 14 is charged or discharged. As described above, the oscillation frequency of the voltage controlled oscillator 12 is determined by its input voltage level. Therefore, by selecting the LPF 14 having the desired voltage level, the voltage controlled oscillator 12
By applying this voltage level to , the corresponding desired oscillation frequency can be obtained.

Therefore, the voltage level at which the LPF 14 is charged may be set in accordance with the predetermined frequency range of the input signal (1). That is, the above assumed frequency range may be divided into N stages, and each LPF 14 may be charged with a voltage level corresponding to each frequency.

With this setting, the frequency detection circuit 11 uses two analog switches SW1. By appropriately selecting and controlling SW2 to select an LPF 14 having an appropriate voltage level, the oscillation frequency of the voltage controlled oscillation 'a12 can be adjusted to the input signal 11.
can be set to a value close to the frequency of

On the other hand, as described above, the phase comparator 13 detects the phase difference between the output signal C1 of the voltage controlled oscillator 12 and the input signal 11, applies the corresponding DC voltage to the analog switch SW1, and supplies the analog switch SW1 with a frequency detection circuit. The oscillation frequency of the voltage controlled oscillator 12 is controlled via the LPF 14 selected by the voltage controlled oscillator 11 and the analog switch SW2. In this way, the input signal 11 and the output signal C1 are synchronized.

tjS2 is a timing chart for explaining the operation of the PLL circuit 10. The PLL circuit 10 has a frequency of 11 until time to, as shown in FIG.
The PLL circuit 10 is locked by constantly inputting the input signal 11 having
Assuming that the frequency f1 changes to the frequency f2,
The operation of the PLL circuit 10 will be explained.

Until time 10, the PLL circuit 10 is locked at the frequency f1, so the oscillation frequency of the voltage controlled oscillator 12 is set equal to the frequency f1 of the input signal 11. That is, the period of the output signal C1 of the voltage controlled oscillator 12 is set equal to the period T1 of the input signal generator 1.

In order to lock the oscillation frequency of the voltage controlled oscillator 12 to the frequency 11 as described above, a corresponding input voltage level v1 is required. Therefore, (5) LPF 7 having voltage level ■1 shown by line L1 shown in the figure.
1 is selected (see (3) in the same figure), and this LPF
71 output voltage level ■1 is given to the voltage controlled oscillation n12 via the analog switch SW2 (see (6) in the same figure).
), thereby the voltage controlled oscillator 12 outputs an output signal C1 having an oscillation frequency equal to the frequency r1 of the input signal 11.

Next, when the frequency of the input signal 11 changes at time to, the frequency detection circuit 11 detects the frequency f2 that changed at time t1, and immediately switches the analog switch S
The LPF 72 is selected by controlling WI and SW2. This is because the LPF 72 holds the output voltage level ■2 in advance as shown in the line L2 shown in FIG. This is because it has a level that can be controlled to a size close to .

Therefore, the frequency detection circuit 11 selects the LPF 72 that holds this voltage level (2) via the two analog switches SWI and SW2, so that the voltage level (2) is immediately applied to the voltage controlled oscillator 12. As a result, the input voltage level of the voltage controlled oscillator 12 to which the voltage level ■1 of the LPF /1 is inputted is as follows.
At time t1, two voltage levels V1. The voltage level difference ΔV with V2 is instantaneously added to the voltage level ■1.

The voltage controlled oscillator 12 to which the voltage level v2 is inputted in this manner immediately controls its oscillation frequency to a level close to the changed frequency r2.

After this, at time t2, the phase comparator 313 detects the phase difference between the input signal generator 1 and the output signal C1, and converts the corresponding DC voltage PV1 into the LPFJ! 2 (see (4) in the figure), and the phase comparator 13 is kept at high impedance until time t2.

The LPF 72 is charged by the DC voltage PV1 and its output voltage level increases, which causes the voltage controlled oscillator 1 to increase.
given to 2. Corresponding to this increased input voltage level, the oscillation frequency of the voltage controlled oscillator 12 increases, and the phase difference between the two signals decreases. Furthermore, at time t3, the phase comparator 13 outputs a DC voltage PV2 corresponding to the phase difference.
, the voltage controlled oscillator 1 at time t4
2 is given a further increased input voltage level V2m,
At time t5, the two signals are synchronized, and from then on, the PLL circuit 10 is locked in this state.

Note that even after time t1, the LPF 1 maintains the voltage level 1 unless the LPF 71 is selected again by the analog switches SWI and SW2. Also, the LPFJ? 2 also holds the increased voltage level V2a after time t4 unless the LPF /2 is selected.

Therefore, after time t4, LPF! 2 is selected, the increased voltage level V2a will be applied to the voltage controlled oscillator 12.

As described above, in the PLL circuit 10 of this embodiment, even if the frequency of the input signal 11 changes, by selecting the desired LPF 14, the oscillation frequency of the voltage controlled oscillator 12 is instantly controlled to the changed frequency. As a result, the lock time can be significantly shortened.

Effects As described above, in the phase-locked loop circuit according to the present invention, the calculation means corresponding to the frequency of the first signal detected by the frequency detection means is selected, and the output level held by this calculation means is determined by the oscillation means. given to.

Therefore, the oscillation frequency of the oscillation means is set to a value close to the frequency of the first signal. When the frequency of the first signal inputted by the frequency detection means is detected in this way, a second signal having an oscillation frequency close to the frequency of the first signal is detected.
Since the signal is immediately output from the oscillation means, the lock time in the PLL circuit is significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the electrical configuration of a PLL circuit 10 which is an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the PLL circuit 10, and FIG. 3 is a typical prior art. FIG. 144 is a block diagram showing the electrical configuration of the PLL circuit 1, and FIG. 144 is a timing chart for explaining the operation of the PLL circuit 1 of the prior art.

Claims (1)

[Claims] Frequency detection means for detecting the frequency of an input first signal; oscillation means for outputting a second signal having an oscillation frequency corresponding to the input voltage level; and a first signal and a second signal. and a phase difference detection means that detects a phase difference between the two and outputs a voltage level corresponding to this phase difference. A plurality of calculation means are provided for calculating the output level from the phase difference detection means and each holding the output level, and each calculation means is connected in parallel, and the frequency of the first signal detected by the frequency detection means is Correspondingly, either one
The first calculation means is selected and connected to the phase difference detection means.
A phase-locked loop circuit comprising: a switching means; and a second switching means for connecting the selected arithmetic means and the oscillation means.