JPS63191718U - - Google Patents
Info
- Publication number
- JPS63191718U JPS63191718U JP8142787U JP8142787U JPS63191718U JP S63191718 U JPS63191718 U JP S63191718U JP 8142787 U JP8142787 U JP 8142787U JP 8142787 U JP8142787 U JP 8142787U JP S63191718 U JPS63191718 U JP S63191718U
- Authority
- JP
- Japan
- Prior art keywords
- potential point
- current
- current amplification
- alternating signal
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims 5
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Amplifiers (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図はこの発明の一実施例の構成を示す回路
図、第２図は第１図に示す回路の動作を説明する
ために示す信号波形図、第３図はエミツタフオロ
ア回路の構成を示す回路図である。
１……入力端子、２……電源端子、３……制御
端子、４……端子、５……出力端子、Ｔｒ１，Ｔ
ｒ２，Ｔｒ３……トランジスタ、Ｒ１，Ｒ２，Ｒ
３……抵抗、ＳＷ１……スイツチ。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a signal waveform diagram shown to explain the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing the configuration of an emitter follower circuit. It is a diagram. 1...Input terminal, 2...Power terminal, 3...Control terminal, 4...Terminal, 5...Output terminal, Tr1, T
r2, Tr3...transistor, R1, R2, R
3...Resistance, SW1...Switch.
Claims (1)
の直流レベルをもつ交番信号を電流増幅する第１
の電流増幅手段と、 上記第１の電位点および、この第１の電位点と
上記基準電位点の間に位置する第２の電位点との
間に配置され、上記交番信号を電流増幅する第２
の電流増幅手段と、 上記交番信号のレベルが上記基準電位点と上記
第２の電位点との間にある期間は、上記第１の電
流増幅手段をオン状態、第２の電流増幅手段をオ
フ状態とし、上記交番信号のレベルが上記第２の
電位点と上記第１の電位点との間にある期間は、
上記第１の電流増幅手段をオフ状態、上記第２の
電流増幅手段をオン状態とする制御手段とを具備
したことを特徴とする電流増幅回路。[Claims for Utility Model Registration] A first device that is placed between a first potential point and a reference potential point and that current amplifies an alternating signal having a predetermined DC level.
and a current amplifying means disposed between the first potential point and a second potential point located between the first potential point and the reference potential point, for current amplifying the alternating signal. 2
and a period in which the level of the alternating signal is between the reference potential point and the second potential point, the first current amplification means is turned on and the second current amplification means is turned off. state, and the period during which the level of the alternating signal is between the second potential point and the first potential point,
A current amplification circuit comprising: control means for turning off the first current amplification means and turning on the second current amplification means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8142787U JPS63191718U (en) | 1987-05-28 | 1987-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8142787U JPS63191718U (en) | 1987-05-28 | 1987-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63191718U true JPS63191718U (en) | 1988-12-09 |
Family
ID=30933154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8142787U Pending JPS63191718U (en) | 1987-05-28 | 1987-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63191718U (en) |
-
1987
- 1987-05-28 JP JP8142787U patent/JPS63191718U/ja active Pending
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