JPS63185315U - - Google Patents
Info
- Publication number
- JPS63185315U JPS63185315U JP1987077177U JP7717787U JPS63185315U JP S63185315 U JPS63185315 U JP S63185315U JP 1987077177 U JP1987077177 U JP 1987077177U JP 7717787 U JP7717787 U JP 7717787U JP S63185315 U JPS63185315 U JP S63185315U
- Authority
- JP
- Japan
- Prior art keywords
- amplitude
- output
- slope
- steps
- limiters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
本考案の実施例に使用した振幅制限器の入力振幅
対出力振幅特性、第３図は本考案の一実施例の波
形図、第４図は本考案の他の実施例の回路図、第
５図は本考案の一実施例及び従来の振幅制限回路
が得ようとする特性図、第６図は従来の振幅制限
器の回路図、第７図はハード及びソフトリミツタ
の波形図である。
２，３……振幅制限器、Ｑ１，Ｑ２，Ｑ３，Ｑ
４……ＰＮＰトランジスタ。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an input amplitude vs. output amplitude characteristic of the amplitude limiter used in the embodiment of the invention, and Fig. 3 is a waveform diagram of an embodiment of the invention. , Fig. 4 is a circuit diagram of another embodiment of the present invention, Fig. 5 is a characteristic diagram to be obtained by an embodiment of the present invention and a conventional amplitude limiting circuit, and Fig. 6 is a diagram of a conventional amplitude limiter. The circuit diagram, FIG. 7, is a waveform diagram of the hard and soft limiters. 2, 3... Amplitude limiter, Q 1 , Q 2 , Q 3 , Q
4 ...PNP transistor.
Claims (1)
上の傾斜で変化する特性をもつ振幅制限回路にお
いて、 各々２段階の傾斜を有し、かつ、互いに異なる
入力振幅対出力振幅特性をもち、同一の入力信号
の振幅制限を行なう複数の振幅制限器と、該複数
の振幅制限器より並列に取り出された各出力信号
を夫々加算して該振幅制限回路の出力とする加算
器とよりなる振幅制限回路。[Claims for Utility Model Registration] An amplitude limiting circuit having a characteristic in which the input amplitude vs. output amplitude characteristic changes with a slope of at least three or more steps, each having a slope of two steps and different input amplitude vs. output amplitudes. a plurality of amplitude limiters that have characteristics and limit the amplitude of the same input signal; and an adder that adds each output signal taken out in parallel from the plurality of amplitude limiters as an output of the amplitude limiter. An amplitude limiting circuit consisting of.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987077177U JPS63185315U (en) | 1987-05-22 | 1987-05-22 | |
| US07/195,585 US4860105A (en) | 1987-05-22 | 1988-05-18 | Noise Reducing circuit of a video signal |
| DE88304624T DE3879758T2 (en) | 1987-05-22 | 1988-05-20 | Circuit for reducing the noise of a video signal. |
| EP88304624A EP0292324B1 (en) | 1987-05-22 | 1988-05-20 | Noise reduction circuit of a video signal |
| DE198888304624T DE292324T1 (en) | 1987-05-22 | 1988-05-20 | CIRCUIT FOR REDUCING NOISE OF A VIDEO SIGNAL. |
| KR1019880006013A KR920001004B1 (en) | 1987-05-22 | 1988-05-21 | Emphasis Circuit |
| US07/209,650 US4864404A (en) | 1987-05-22 | 1988-06-21 | Noise reduction circuit of a video signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987077177U JPS63185315U (en) | 1987-05-22 | 1987-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185315U true JPS63185315U (en) | 1988-11-29 |
Family
ID=30924941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987077177U Pending JPS63185315U (en) | 1987-05-22 | 1987-05-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185315U (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153816A (en) * | 1980-04-30 | 1981-11-28 | Toshiba Corp | Signal processing circuit |
| JPS56161708A (en) * | 1980-05-19 | 1981-12-12 | Toshiba Corp | Signal processing circuit |
| JPS56161707A (en) * | 1980-05-19 | 1981-12-12 | Toshiba Corp | Signal processing circuit |
| JPS59127412A (en) * | 1983-01-12 | 1984-07-23 | Nec Corp | Logarithmic compressing and amplifying circuit |
| JPS6066511A (en) * | 1983-09-22 | 1985-04-16 | Nec Corp | Logarithmic compression amplifying circuit |
-
1987
- 1987-05-22 JP JP1987077177U patent/JPS63185315U/ja active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56153816A (en) * | 1980-04-30 | 1981-11-28 | Toshiba Corp | Signal processing circuit |
| JPS56161708A (en) * | 1980-05-19 | 1981-12-12 | Toshiba Corp | Signal processing circuit |
| JPS56161707A (en) * | 1980-05-19 | 1981-12-12 | Toshiba Corp | Signal processing circuit |
| JPS59127412A (en) * | 1983-01-12 | 1984-07-23 | Nec Corp | Logarithmic compressing and amplifying circuit |
| JPS6066511A (en) * | 1983-09-22 | 1985-04-16 | Nec Corp | Logarithmic compression amplifying circuit |
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