JPS63184990A - semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory, and more particularly to a sense amplifier section that detects and amplifies a bit line potential difference.

(Prior Art) In a semiconductor memory, such as a static RAM (random access memory), in order to detect and amplify the potential difference between the B and T lines, a current mirror type sensor as shown in FIG. 6 has conventionally been used. An amplifier SA is provided. This sense amplifier SA connects a pair of bit lines B.
For differential amplification (for input) with each f-} connected to L and BL
N-channel MOS } transistor N1 r N 2
and P-channel MOS transistors P1+P2 for load, which are connected in a power and current mirror manner. Furthermore, two inverters 11+I! for the latch circuit LA are connected to the connection point (output node) between the amplifying transistor N2 and the load transistor P2. is connected.

Note that vDD is the high potential side power supply voltage, and VSS is the low potential side (
Ground potential side) is the power supply voltage.

In the sense amplifier SA, in the activated state, wasteful through current flows even after sensing and amplifying the bit line potential difference and reading data from the memory cell. The through current of jin is
If the memory does not have an auto power down mode, the current will continue to flow even after data is output, and even if there is an auto power down mode, the current will continue to flow until this Mote 9 is reached, resulting in the problem of increased current consumption in the memory read mode. there were.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problem that the current consumption increases due to the through current after reading data of the sense amplifier in the read mode. An object of the present invention is to provide a semiconductor memory that can reduce the through current after reading out the f-tater and reduce the current consumption in the read mode.

[Structure of the Invention] (Means for Solving Problems) The semiconductor memory of the present invention suppresses the output data of the sense amplifier by using the output data of the sense amplifier that detects and amplifies the bit line potential difference. It is characterized by being provided with a circuit for feedback control.

(Function) After data is output from the sense amplifier in the read mode, the output can be used to suppress the through current of the sense amplifier, so it is possible to reduce power consumption in the read mode.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a current mirror type sense amplifier section for detecting and amplifying the bit line potential difference provided in the static RAM K. That is, a current mirror type sense amplifier SA and a switching N-channel MOS transistor N3 are connected in series between the %VDD power supply node and the Vall power supply node (ground terminal). The sense amplifier SA includes an N-channel MO8) transistor N1 for differential amplification (input), in which each date is connected to a pair of no bit lines BL, BL, and each source is commonly connected.
N2, and a current mirror-connected P-channel MO8) Lanzo star P1+P2 which serves as a load for this transistor N1 t N 2 . The drain interconnection point between the amplifying N-channel transistor P2 and the load P-channel transistor P2 (the input terminal and output terminal of the two inverters Z1 and I2 are connected to the sense amplifier output terminal). It's going to be done.

A child circuit LA is connected. In this way, the output terminal of the child circuit LA is connected to the r-to of the N-channel transistor N3 for the switch, and the pull-up P-channel MO8) Lanzo transistor P is connected between this gate and the VDD power supply node.
3 is connected, and this P channel transistor P3
A precharge signal 7t is sent to the dirt at a predetermined timing.
d is given. This precharge signal ('td) becomes active (low level) when the memory address input changes.

Next, the operation of the sense amplifier section will be explained.

In the memory read mode, the precharge signal <'td becomes low level due to a change in the address input, the pull-up transistor P3 is turned on, and the output terminal of the latch circuit LA becomes high level9, and the switching transistor N3 is turned on. The sense amplifier SA is activated as soon as the signal is turned on. At this time, if the sense amplifier output node becomes a high level when the memory cell data read to the bit line pair BL, BL is 'l', the output of the latch circuit LA is latched to a low level, The switching transistor N3 is turned off and the sense amplifier SA becomes inactive. That is, when the address input changes and memory cell data 1" is read, the sense amplifier SA
After A detects and amplifies the cell data, and the latch circuit LA latches and outputs the data, the sense amplifier fsA is deactivated using the CH output, so the through current of the sense amplifier SA is reduced. However, the current consumption in the memory read mode is reduced. Note that in the above case, when the memory cell data 0'' is read, the sense amplifier output node remains at a low level, the output of the latch circuit LA is latched at a high level, and the switching transistor N3 remains on. The sense amplifier SA remains activated as in the conventional example.Furthermore, if the output of the latch circuit LA is at a high level when the address input changes,
Sense Anne 7'SA has already been activated.

2 to 5 show sense amplifier sections according to other embodiments, respectively. That is, compared to the sense amplifier section described above with reference to FIG. 1, the sense amplifier section in FIG. 2 has a P-channel transistor P4 inserted between the VDD ia source node and the sense amplifier SA as a switching transistor. , instead of the pull-up transistor, a pull-down N-channel transistor N4 is inserted between the dirt of the switch transistor P4 and the ground terminal, and a 7' recharge signal φtd (address The difference is that a high-level active state is applied depending on a change in the input, but other parts are the same as in FIG. 1 and are designated by the same reference numerals. According to the sense amplifier section shown in FIG. 2 above, when the address input changes and new cell data is read, the nori charge signal φtd becomes high level, the pull-down transistor N4 is turned on, and the output of the latch circuit LA is turned on. The level becomes low, the switching transistor P4 is turned on, and the sense amplifier SA is activated. Note that if the output of the circuit LA is at a low level when the address input changes, the sense amplifier SA has already been activated. Then, if the sense amplifier output node becomes low level when the newly read cell data is NOH, the output of the latch circuit LA is latched to high level, the switching transistor P4 is turned off, and the sense amplifier output node becomes low level. SA becomes inactive.

As a result, the through current of the sense amplifier 7'SA is reduced, and the current consumption in the memory read mode is reduced. In the above case, when the memory cell data 11'' is read, the sense amplifier output node is not at a high level, and the output of the latch circuit LA is latched at a low level.
The switching transistor P4 remains on, and the sense amplifier SA remains activated as in the conventional example.

The sense amplifier section in FIG. 3 differs from the sense amplifier section in FIG. 1 in that the output terminal of the latch circuit LA and the switch transistor N3 are not connected to each other; The difference is that an inverter I3 is connected between N3 and the dart, but the rest is the same. According to the sense amplifier section shown in FIG. 3, a change in the address input causes a pull-up of υ by the si-recharge signal itd.

The switching transistor P3 is not turned on, the output terminal of the inverter 3 becomes high level, and the switching transistor N
3 is turned on and the sense amplifier SA is activated. Note that if the input terminal of the latch circuit LA is at a low level at this time, the output terminal of the inverter 3 is at a high level, so that the sense amplifier SA has already been activated. Furthermore, if the input terminal of the latch circuit LA is at high level at this time, a through current flows from the pull-up transistor P3 toward the output terminal of the inverter 3 (low level at this time); In order to prevent the voltage from increasing, and to keep the output terminal of the inverter 3 at a high level and keep the sense amplifier SA in an activated state until the sense amplifier 7'SA outputs correct data, the ground potential inside the inverter is The channel width W of an N-channel transistor (not shown) connected to the side is set to be sufficiently small. And bit a vs. B
If the sense amplifier output node becomes high level when the memory cell data read to L and BL is 1", the inverter outputs the signal after the precharge signal φtd becomes inactive (high level here). The output of E3 becomes low level, the switching transistor N3 is turned off, and the sense amplifier fsA becomes inactive.In the above case, when the memory cell data "0" is read, the sense amplifier output node is not at a low level, the output of the inverter 3 is at a high level, the switching transistor N3 remains on, and the sense amplifier SA remains activated as in the conventional example.
The sense amplifier section has f+) charso signal 'l't
While d is at a low level, the sense amplifier SA is activated to read memory cell data, and when the read data is °1, the precharge signal ("When td returns to high level, the switch transistor N3 is turned off. to suppress through current.

Compared to the sense amplifier section in FIG. 2, the sense amplifier' section in FIG. 4 does not connect the output end of the latch circuit LA to the dart of the switching transistor P4, and
The difference is that an inverter I4 is connected between the output terminal of the switch transistor P4 and the switch transistor P4, but the other features are the same. According to the sense amplifier section shown in FIG. 4, the pull-down transistor N4 is turned on by the precharge signal φtd due to a change in the address input, the output terminal of the inverter 4 becomes low level, and the switch transistor P4 is turned on. Sense amplifier SA is activated. Note that if the input terminal of the latch circuit LA is at high level at this time, the output terminal of the inverter 4 is at low level, so that the sense amplifier SA has already been activated. Furthermore, if the input terminal of the latch circuit LA is at a low level at this time, the output terminal of the inverter 4 (at a high level at this time) is directed toward the pull-down transistor N4.
In order to prevent this through current from becoming large, and from the sense amplifier 7'SA
In order to keep the output terminal of the inverter 4 at a low level and keep the sense amplifier SA in an activated state until outputting correct data, a P-channel transistor (not shown) is connected to the power supply potential side of the inverter. Set the channel @W sufficiently small. Then, the memory cell data read to the bit line pair BL, BL is “0”
If the sense amplifier output node becomes low level when
The output becomes high level, the switching transistor P4 is turned off, and the sense amplifier 7'SA becomes inactive. In the above case, when the memory cell data '1' is read, the sense amplifier output node becomes high level, the output of inverter 4 becomes low level, and the switching transistor P4 is turned on! The sense amplifier SA remains activated like the conventional flj. That is, the sense amplifier section activates the sense amplifier SA to read memory cell data while the precharge signal φtd is at a high level. When the read data is '0'' and the nori charge signal φtd returns to low level, the switching transistor Pt'fc
Turn off to suppress through current.

The sense amplifier section in FIG. 5 differs from the sense amplifier section in FIG. 3 in the same way as the sense amplifier section in FIG. '
An inverter 5 for td inversion is additionally connected, and the sense amplifier fSA'i can be made inactive even when 1" or 0" of memory cell data is read.

In each of the above embodiments, a current mirror type sense amplifier is shown, but the present invention can be applied to other sense amplifiers.

[Effects of the Invention] As described above, according to the semiconductor memory of the present invention, after data is output from the sense amplifier in the read mode, the output can be used to deactivate the sense amplifier. Lower power consumption can be achieved. It is also advantageous that there is no need to set a pulse to deactivate the sense amplifier in accordance with the time from when the address input changes until the sense amplifier outputs data. Therefore, as the capacity of the memory increases and the number of sense amplifiers increases, the effects of the present invention become more significant.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the sense amplifier section in one embodiment of the semiconductor memory of the present invention, FIGS. 2 to 5 are circuit diagrams showing the sense amplifier section in other embodiments, and FIG.
The figure is a circuit diagram showing a sense amplifier section in a conventional semiconductor memory. BL, BL...pit line pair, SA...sense amplifier, LA...latch circuit, N3 #P4...switch transistor, P3...sol-up transistor, N4...pull-down transistor ,I3+
Z4+■5...Inverter. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 4 Figure 50 Figure 6

Claims (3)

[Claims] (1) It is characterized by comprising a sense amplifier that detects and amplifies the bit line potential difference, and a circuit that performs feedback control so as to suppress the through current of the sense amplifier using the output data of the sense amplifier. semiconductor memory. (2) In order to suppress the through current of the sense amplifier,
An N-channel transistor for switching is inserted on the ground potential side of the sense amplifier, or a P-channel transistor for switching is inserted on the power supply potential side of the sense amplifier, or the N-channel transistor for switching and P
2. The semiconductor memory according to claim 1, wherein the semiconductor memory comprises both channel transistors. (3) The semiconductor memory according to claim 1 or 2, wherein the sense amplifier is of a current mirror type.