[go: up one dir, main page]

JPS63184330A - Baking device for photoresist - Google Patents

Baking device for photoresist

Info

Publication number
JPS63184330A
JPS63184330A JP1571587A JP1571587A JPS63184330A JP S63184330 A JPS63184330 A JP S63184330A JP 1571587 A JP1571587 A JP 1571587A JP 1571587 A JP1571587 A JP 1571587A JP S63184330 A JPS63184330 A JP S63184330A
Authority
JP
Japan
Prior art keywords
wafer
photoresist
hot plate
resist
hot plates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1571587A
Other languages
Japanese (ja)
Inventor
Makoto Tominaga
誠 富永
Mamoru Yamada
守 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1571587A priority Critical patent/JPS63184330A/en
Publication of JPS63184330A publication Critical patent/JPS63184330A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To set temperature distribution in a wafer surface arbitrarily, and to equalize the pattern size of a semiconductor device in the wafer surface by concentrically dividing, separating and disposing a plurality of ring-shaped hot plates having different diameters and mounting severally driven heat sources to each hot plate. CONSTITUTION:A plurality of ring-shaped hot plates 11, 12...1n having different diameters are divided, separated and arranged concentrically, severally driven heat sources 21, 22...2n are set up to respective hot plate 11, 12...1n, a plurality of the hot plates 11, 12...1n having different diameters are brought into contact with a wafer 3, the temperatures of each heat source 21, 22...2n are controlled, and the wafer 3 is heated by the hot plates 11, 12...1n. Since the sensibility of a photoresist generally changes by the temperature of pre-baking, the size of a resist pattern is distributed in the wafer by varying the sensibility of the resist in the wafer, thus equalizing size after etching.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体製造プロセスで用いられるフォトレジス
トのプリベーク、特にホットプレート式のベーク装置に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to prebaking of photoresists used in semiconductor manufacturing processes, and particularly to a hot plate type baking apparatus.

〔従来の技術〕[Conventional technology]

従来のフォトレジストのホットプレート装置によるプリ
ベーク方法は、通常上としてフォトレジスト中に含有さ
れている溶剤の蒸発を目的とし、ウェハー内の温度分布
が均一になるように、ウェハーの裏面全面あるいは一部
に接触するホットプレートを特定の温度で保温状態にし
ておき、ウェハーを吸着していたが、このホットプレー
トは1個につき1個の熱源で均一な温度で保温されてい
た。
Conventional photoresist pre-baking methods using hot plate equipment aim to evaporate the solvent contained in the photoresist, and the wafer is heated completely or partially on the back side of the wafer so that the temperature distribution within the wafer is uniform. A hot plate in contact with the wafer was kept at a specific temperature to adsorb the wafers, but each hot plate was kept at a uniform temperature by a single heat source.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のホットプレート装置によるプリベーク方
法では、フォトレジストの感度がウェハー面内で常に均
一に保持されていたが、このことが、半導体製造プロセ
スにおいて次のような欠点をもたらしていた。すなわち
、半導体製造プロセスにおけるフォトレジストを用いた
フォトリソグラフィ一工程は次に示す大きく2種に大別
される工程を伴っている。第1はリソグラフィーにより
形成されたフォトレジストパターンにより、レジストの
下地を選択的にエツチングする場合で、第2は形成され
たフォトレジストパターンをマスクにイオン注入する場
合である。前者の場合、獲得されるパターンは、エツチ
ング特性に大きく影響されるが、後者の場合はフォトレ
ジストのパターンだけが、パターン(イオン注入領域)
を決定する。
In the above-mentioned conventional pre-bake method using a hot plate device, the sensitivity of the photoresist is always maintained uniformly within the wafer surface, but this brings about the following drawbacks in the semiconductor manufacturing process. That is, one step of photolithography using a photoresist in a semiconductor manufacturing process involves steps roughly classified into two types as shown below. The first is when a resist base is selectively etched using a photoresist pattern formed by lithography, and the second is when ions are implanted using the formed photoresist pattern as a mask. In the former case, the pattern obtained is strongly influenced by the etching properties, while in the latter case only the pattern of the photoresist is affected by the pattern (ion implantation region).
Determine.

ここで、ウェハー上に多数の同一特性の半導体装置を形
成するためには、上記の後者の場合はフォトレジストの
パターン寸法をウェハー面内で均一にすることが必要で
あるが、前者の場合はエツチング後の寸法が均一になら
なければいけない。
In order to form a large number of semiconductor devices with the same characteristics on a wafer, in the latter case, it is necessary to make the photoresist pattern dimensions uniform within the wafer surface, but in the former case, it is necessary to make the pattern dimensions of the photoresist uniform within the wafer surface. The dimensions after etching must be uniform.

従来のフォトレジストのプリベーク方法では、ウェハー
面内のフォトレジストの感度が常に均一になるので、ウ
ェハー面内のレジストパターン寸法は均一になるが、フ
ォトレジストパターンにより下地の選択的エツチングを
伴う場合獲得されるパターンは、エツチング特性により
ウェハー面内で寸法のばらつきを生じてしまうという欠
点がある。
In the conventional photoresist pre-baking method, the sensitivity of the photoresist within the wafer plane is always uniform, so the resist pattern dimensions within the wafer plane are uniform, but when the photoresist pattern involves selective etching of the underlying layer, The etched pattern has the disadvantage that it causes dimensional variations within the wafer surface due to etching characteristics.

本発明の目的はウニへ−面内での温度分布を任意に設定
可能なフォトレジストのベーク装置を提供することにあ
る。
An object of the present invention is to provide a photoresist baking device that can arbitrarily set the temperature distribution within the surface of a sea urchin.

〔発明の従来技術に対する相違点〕[Differences between the invention and the prior art]

上述した従来のホットプレート装置によるプリベーク方
法に対し、本発明のホットプレート式プリベーク装置は
ウェハー面内に同心円状の温度分布を持たせることので
きる形状の熱源を有することにより、レジストの感度を
ウェハー内で分布を持たせることができる。このレジス
トの感度をウェハー内で変化させることによりレジスト
パターン寸法をウェハー内で分布させ、エツチング後の
寸法を均一にすることができ、またフォトレジストのパ
ターン寸法だけで、パターン形成がされる場合にはホッ
トプレートの温度分布を均一にすることにより、レジス
トパターン寸法を均一にすることができる。以上のよう
に本発明はフォトレジストのプリベーク温度をウェハー
内で同心円状に自由に分布させることができるという独
創的内容を有する。
In contrast to the pre-bake method using the conventional hot plate apparatus described above, the hot plate pre-bake apparatus of the present invention has a heat source shaped to provide a concentric temperature distribution within the wafer surface, thereby improving the sensitivity of the resist on the wafer. It is possible to have a distribution within. By changing the sensitivity of this resist within the wafer, the resist pattern dimensions can be distributed within the wafer and the dimensions after etching can be made uniform. By making the temperature distribution of the hot plate uniform, the resist pattern dimensions can be made uniform. As described above, the present invention has an original content in that the prebaking temperature of the photoresist can be freely distributed concentrically within the wafer.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は半導体製造プロセスのフォトレジストをホット
プレートにて加熱するベーク装置において、複数個の異
径のリング状ホットプレートを同心円状に分割独立させ
て配設し、各ホットプレートに個々に駆動される熱源を
装備したことを特徴とするフォトレジストのベーク装置
である。
The present invention is a baking device that heats photoresist using a hot plate in a semiconductor manufacturing process, in which a plurality of ring-shaped hot plates with different diameters are arranged concentrically and independently, and each hot plate is individually driven. This is a photoresist baking device characterized by being equipped with a heat source.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

半導体製造プロセスにおいて、リソグラフィーにより形
成されたフォトレジストパターンにより、レジストの下
地を選択的にエツチングする場合、エツチング後のパタ
ーン寸法は、フォトレジストのパターン寸法が面内で均
一な場合にもエツチング特性の影響により、特に下地が
Po1ySi (多結晶シリコン)で、ドライエッチを
行うときなど第4図の実線のようにウェハー内でウェハ
ー中心を対称中心に寸法分布を示す。これがプロセス中
の異常によるものではなく、例えば第4図の点線に示す
エツチング装置特有のエツチングレートの面内ばらつき
のような、プロセス固有の本質的な要因によるものであ
る場合、レジスト寸法を第7図のようにエツチング後の
寸法と逆に分布させられれば、互いに打ち消し合いエツ
チング後のレジスト下地のパターン寸法は、第8図のよ
うにウェハー面内で均一にすることができる。
In the semiconductor manufacturing process, when the base of the resist is selectively etched using a photoresist pattern formed by lithography, the pattern dimensions after etching will vary depending on the etching characteristics even if the pattern dimensions of the photoresist are uniform within the plane. Due to this influence, especially when dry etching is performed when the base is PolySi (polycrystalline silicon), the wafer exhibits a dimensional distribution symmetrically about the wafer center, as shown by the solid line in FIG. If this is not due to an abnormality during the process, but is due to an essential factor unique to the process, such as the in-plane variation in etching rate peculiar to the etching apparatus shown by the dotted line in FIG. If the distribution is opposite to the dimension after etching as shown in the figure, they will cancel each other out, and the pattern dimension of the resist base after etching can be made uniform within the wafer surface as shown in FIG.

ところで、フォトレジストは一般的にプリベーク温度に
よって感度が第5図のように変化する。
Incidentally, the sensitivity of a photoresist generally changes depending on the prebaking temperature as shown in FIG.

そこでプリベーク温度を第3図の実線のようにウェハー
内で分布させられれば、ウェハー面内のレジスト寸法を
第7図のように分布させることができ、エツチング寸法
がウェハー面内で第8図のように均一になると考えられ
る。
Therefore, if the prebake temperature can be distributed within the wafer as shown by the solid line in Figure 3, the resist dimensions within the wafer plane can be distributed as shown in Figure 7, and the etching dimensions can be distributed within the wafer plane as shown in Figure 8. It is thought that it will be uniform.

本発明は第1図、第2図に示すように複数個の異径のリ
ング状ホットプレート11,1□・・・1nを同心円状
に分割独立させて配設し、各ホットプレート11.1□
・・・1nに個々に駆動される熱源2□、22・・・2
nを装備し、ウェハー3に複数個の異径ホットプレート
1□112・・Inを接触させ各熱源21,2□・・・
2nの温度をコントロールしてウェハー3をホットプレ
ート11゜12・・・1nにて加熱するようにしたもの
である。
As shown in FIGS. 1 and 2, a plurality of ring-shaped hot plates 11, 1 . □
...1n heat sources 2□, 22...2 individually driven
A plurality of hot plates 1□112...In of different diameters are brought into contact with the wafer 3, and each heat source 21, 2□...
The wafer 3 is heated by hot plates 11°, 12, . . . 1n while controlling the temperature of 2n.

(実施例1) 上述したようにフォトレジストは一般的にプリベーク温
度によって感度が第5図のように変化するから、プリベ
ーク温度を第3図の実線のようにウェハー内に分布させ
れば、ウェハー面内のレジスト寸法は第7図のように分
布し、エツチング寸法をウェハー面内で第8図のように
均一にすることができる。そこで、本実施例の場合は同
心円状に配列したリング状ホットプレート11・・・1
nのうち中心のホットプレート11を約80℃に温度設
定し、外周側に向けて各ホットプレート12・・・1n
の設定温度を上昇させて第3図の実線で示すような温度
分布を形成させる。
(Example 1) As mentioned above, the sensitivity of photoresist generally changes depending on the pre-bake temperature as shown in Fig. 5, so if the pre-bake temperature is distributed within the wafer as shown by the solid line in Fig. 3, the wafer The in-plane resist dimensions are distributed as shown in FIG. 7, and the etching dimensions can be made uniform within the wafer plane as shown in FIG. 8. Therefore, in the case of this embodiment, the ring-shaped hot plates 11...1 are arranged concentrically.
Set the temperature of the center hot plate 11 at about 80°C, and set the temperature of each hot plate 12...1n toward the outer periphery.
The set temperature is increased to form a temperature distribution as shown by the solid line in FIG.

(実施例2) 次に実施例2について説明する。フォトレジストでパタ
ーンを形成し、それをマスクにイオン注入する場合、イ
オン注入領域はレジストパターンの寸法だけで決定され
る。この場合は、第3図の点線に示すようにウェハー面
内の温度分布を一定にして、ウェハー面内のレジスト感
度を均一にする必要がある。本実施例では本発明のホッ
トプレート1□〜1nの各温度を同一温度にすればよい
。それにより、ウェハー面内のレジスト寸法を均一にす
ることができ、イオン注入領域はウェハー内で均一にす
ることができる。
(Example 2) Next, Example 2 will be described. When a photoresist pattern is formed and ions are implanted into a mask, the ion implantation area is determined only by the dimensions of the resist pattern. In this case, it is necessary to make the temperature distribution within the wafer surface constant as shown by the dotted line in FIG. 3, and to make the resist sensitivity within the wafer surface uniform. In this embodiment, the temperatures of the hot plates 1□ to 1n of the present invention may be set to the same temperature. Thereby, the resist dimensions within the wafer surface can be made uniform, and the ion implantation region can be made uniform within the wafer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は内外異径のホットプレート
の設定温度を同心円状に自由に温度変化させるため、ウ
ェハー面内のレジストの感度を様々に変化させることに
より半導体製造プロセスにおいて、ウェハー面内の半導
体装置のパターン寸法を均一にすることができる効果が
ある。
As explained above, the present invention allows the set temperature of hot plates with different diameters inside and outside to be freely changed in a concentric manner. This has the effect of making the pattern dimensions of semiconductor devices uniform.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のフォトレジストのホットプレート状プ
リベーク装置の平面図、第2図は同縦断面図、第3図は
本発明のプリベーク装置を用いた実施例の一例を示す温
度分布図、第4図は仮想的なエツチングレートの分布図
、第5図は一般的なレジスト感度のプリベーク温度によ
る変化を示す図、第6図は第3図のような実施例のとき
のウェハー面内のレジスト感度の分布を示す図、第7図
は第6図のような実施例のときのレジストパターン寸法
のウェハー面内分布を示す図、第8図は第3図〜第7図
までの実施例のときのエツチング後のパターン寸法のウ
ェハー面内分布を示す図である。
FIG. 1 is a plan view of a photoresist hot plate pre-baking device of the present invention, FIG. 2 is a longitudinal sectional view thereof, and FIG. 3 is a temperature distribution diagram showing an example of an embodiment using the pre-baking device of the present invention. FIG. 4 is a hypothetical etching rate distribution diagram, FIG. 5 is a diagram showing the change in general resist sensitivity due to pre-bake temperature, and FIG. A diagram showing the distribution of resist sensitivity; FIG. 7 is a diagram showing the in-wafer distribution of resist pattern dimensions in the example shown in FIG. 6; FIG. 8 is an example of the embodiments shown in FIGS. 3 to 7. FIG. 4 is a diagram showing the distribution of pattern dimensions within the wafer surface after etching.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体製造プロセスのフォトレジストをホットプ
レートにて加熱するベーク装置において、複数個の異径
のリング状ホットプレートを同心円状に分割独立させて
配設し、各ホットプレートに個々に駆動される熱源を装
備したことを特徴とするフォトレジストのベーク装置。
(1) In a baking device that heats photoresist using a hot plate in a semiconductor manufacturing process, a plurality of ring-shaped hot plates with different diameters are arranged concentrically and independently, and each hot plate is individually driven. A photoresist baking device characterized by being equipped with a heat source.
JP1571587A 1987-01-26 1987-01-26 Baking device for photoresist Pending JPS63184330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1571587A JPS63184330A (en) 1987-01-26 1987-01-26 Baking device for photoresist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1571587A JPS63184330A (en) 1987-01-26 1987-01-26 Baking device for photoresist

Publications (1)

Publication Number Publication Date
JPS63184330A true JPS63184330A (en) 1988-07-29

Family

ID=11896460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1571587A Pending JPS63184330A (en) 1987-01-26 1987-01-26 Baking device for photoresist

Country Status (1)

Country Link
JP (1) JPS63184330A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06333809A (en) * 1993-05-20 1994-12-02 Toshiba Corp Device and method for resist sensitivity adjustment
JPH07111232A (en) * 1993-10-13 1995-04-25 Nec Corp Over for photoresist
JPH08107057A (en) * 1994-10-04 1996-04-23 Hitachi Ltd Baking method and apparatus
JPH1074678A (en) * 1996-08-30 1998-03-17 Fujitsu Ltd Developing method and exposure apparatus
US5950723A (en) * 1995-11-17 1999-09-14 Cvc Products, Inc. Method of regulating substrate temperature in a low pressure environment
JPH11283909A (en) * 1998-03-31 1999-10-15 Dainippon Screen Mfg Co Ltd Substrate heat treating device
JP2000323375A (en) * 1999-05-07 2000-11-24 Mtc:Kk Method and device for heating substrate
JP2000349018A (en) * 1999-06-08 2000-12-15 Nec Corp Bake furnace for photoresist
KR100299258B1 (en) * 1998-06-16 2001-11-30 윤종용 Photoresist Baking Method and Photoresist Baking System
JP2002538501A (en) * 1999-02-22 2002-11-12 ステアーグ ハマテヒ アクチエンゲゼルシャフト Apparatus and method for thermally treating a substrate
JP2009099835A (en) * 2007-10-18 2009-05-07 Toppan Printing Co Ltd Heat treating device for resist-coated substrate, and heat treating method therefor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06333809A (en) * 1993-05-20 1994-12-02 Toshiba Corp Device and method for resist sensitivity adjustment
JPH07111232A (en) * 1993-10-13 1995-04-25 Nec Corp Over for photoresist
JPH08107057A (en) * 1994-10-04 1996-04-23 Hitachi Ltd Baking method and apparatus
US5950723A (en) * 1995-11-17 1999-09-14 Cvc Products, Inc. Method of regulating substrate temperature in a low pressure environment
JPH1074678A (en) * 1996-08-30 1998-03-17 Fujitsu Ltd Developing method and exposure apparatus
JPH11283909A (en) * 1998-03-31 1999-10-15 Dainippon Screen Mfg Co Ltd Substrate heat treating device
KR100299258B1 (en) * 1998-06-16 2001-11-30 윤종용 Photoresist Baking Method and Photoresist Baking System
JP2002538501A (en) * 1999-02-22 2002-11-12 ステアーグ ハマテヒ アクチエンゲゼルシャフト Apparatus and method for thermally treating a substrate
JP2000323375A (en) * 1999-05-07 2000-11-24 Mtc:Kk Method and device for heating substrate
JP2000349018A (en) * 1999-06-08 2000-12-15 Nec Corp Bake furnace for photoresist
JP2009099835A (en) * 2007-10-18 2009-05-07 Toppan Printing Co Ltd Heat treating device for resist-coated substrate, and heat treating method therefor

Similar Documents

Publication Publication Date Title
JPS63184330A (en) Baking device for photoresist
JPH11274030A (en) Resist processing method and apparatus and resist coating method
JP3708786B2 (en) Resist pattern forming method and semiconductor manufacturing system
JP2001274069A5 (en)
US4035226A (en) Method of preparing portions of a semiconductor wafer surface for further processing
JPH0620903A (en) Method for manufacturing semiconductor device
JP2517707B2 (en) Method of forming photoresist pattern
JP3026305B2 (en) Heat treatment method
JPS6347924A (en) Manufacture of semiconductor device
JP2001185471A (en) Heating equipment and method for pattern formation
JP2797321B2 (en) Pyroelectric material heat treatment method
JPS6331118A (en) Baking furnace
JPH0621233Y2 (en) Baking equipment
JP4121770B2 (en) Baking device for photomask manufacturing
KR100712814B1 (en) Wafer Heater and Heating Method
KR100252762B1 (en) Baking condition determining method for photoresist
JPH11243066A (en) Semiconductor device
JPS6254921A (en) Manufacture of semiconductor device
KR20050120493A (en) Heat interference prevention type wafer
JPS62114224A (en) Semiconductor device
JPH01134920A (en) Manufacture of semiconductor device
JP2003178960A (en) Thermal treatment device for substrate
JPH11214279A (en) Substrate heating apparatus
JPH0669125A (en) Semiconductor producing system
JPH04342115A (en) Baking treatment apparatus