JPS63183681A - Storage device - Google Patents

Abstract

PURPOSE:To easily initialize a memory cell by providing a simultaneous selecting means for activating simultaneously plural word lines. CONSTITUTION:In case of the initialization of memory cells 1-16, when a simultaneous selecting signal SELECT is shifted to a high level, OR circuits 100-103 send out an output of a high level to AND circuits 17-20, respectively, irrespective of address signals A0, A1. Subsequently, when the inverse of a precharge signal PG returns to a high level, outputs of the circuits 17-20 are shifted to a high level, and word lines W0-W3 become a high level. As a result, storage nodes N1, N2 of the cells 1-16 are connected electrically to the corresponding pairs of bit lines the inverse of B0, B0- the inverse of B3, B3. In this state, when prescribed initializing data, for instance, '0', '1', '0' and '1' are supplied to inputs D0-D3, and a write signal WR is shifted to a high level, '0' and '1' are written simultaneously in the cells 1-4, 9-12, and 5-8, 13-16, respectively. According, when the line W1 is selected by the signals A0, A1, '0', '1', '0', and '1' appear in outputs O0-O3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and particularly to a storage device such as a single-chip microprocessor.

[Conventional technology]

Random access memory (hereinafter referred to as RAM) is widely used in integrated circuits because it can realize a large storage capacity with a small area compared to other storage elements such as flip-flop circuits. In particular, static RAM is high-speed, and the use of a backup power supply makes it possible to retain data even when the main power source is turned off, so it is used as data memory in single-chip microprocessors.

FIG. 4 shows such a conventional memory device, in which reference numerals 1 to 16 indicate memory cells. Each of the memory cells 1 to 16 includes inverters I, , I connected in parallel and in opposite directions between a pair of storage nodes N, , N2, and a bit line pair BQ between the pair of storage nodes N, , N2 and a bit line pair BQ. ,
It has transfer gates T, , T, provided between BQ to B3 to B3. The operation of writing data into the memory cells 1 to 16 having such a configuration and then reading the data will be described with reference to the timing chart of FIG. 5. First, when the precharge signal PG shifts to low level at time t1, the P-channel MOS
Transistors P1 to P are on/off with each bit line BQ,
BQ~83. B3 is precharged. Subsequently, at time t, the precharge signal PG shifts to high level, and ro and OJ are supplied to the address inputs AQ and Al, and the address decoder 37 outputs its outputs Qo to Q,
Shift the Qo of the target to a high level. As a result, only the inputs of 17 of the AND circuits 17 to 20 become "1, 1", and of the four word lines WO to W3, only WO becomes high level. Therefore, memory cells 1.5, 9.13
The transfer gates T, , T, of each bit line pair BQ, BQ to B3 . The data stored in each memory cell 1, 5, 9, 13 is temporarily read out to B3, and the outputs OQ to 03 are, for example, (0°1.1.
As in 1), K becomes. Here, at time t3, write signal WR
When transitions to a high level, one input of each add circuit 25 to 32 becomes "1", so the data inputs DO to D3
For example, if (0, 0, 0, 0) is supplied to
, 1'', and the N-channel MOS transistor N,
, N, , N, , N, is off, N, , N
, , N, , N are turned on, and the bit lines BO to B3 are grounded. Therefore, memory cells 1, 5,
9. Each storage node N in 13 stores "0",
When the write signal WR shifts to low level at time t4,
“0” in storage nodes N of memory cells 1, 5, 9, and 13
is held. In contrast, time 1. word line W1 to
In the read cycle in which is selected, the memory contents of memory cells 2.6 and 10.14 are output as (1°0.1.1) by time t6 to outputs OO to 03, and word #jl
In the write cycle in which W2 is fully selected, 'for example, (LL1+1) is written into the memory cells 3, 7, 11, and 15 between time t and time t. Another hour 1. In a read cycle in which word @W3 is selected between 11° and 11°, the stored contents of memory cells 4, 8, 12, 16, for example (1, 1, 0, 1) appear at outputs 00 to 03.

In this way, conventional RAM writes data word by word,
In a single-chip microprocessor, it is used to store external input data, decompression data, parameters, etc.

[Problem that the invention seeks to solve]

Generally, in the RAM of a single-chip microprocessor, it is necessary to write certain data into the RAM and initialize it before executing a processing program. If this is executed, each memory cell of the RAM is in a state where undefined data is recorded, so there is a risk that the program will run out of control.

Therefore, it is necessary to prepare a RAM initialization program in advance, but complex programs often have many interrupt factors and may be the first to be executed after the power is turned on. There are many processing routines, and creating a program that initializes all necessary data areas may exceed the designer's attentiveness. Therefore, it is desirable to initialize all data areas in the RAM, but initializing one word of memory cells requires at least one instruction cycle. When writing to each memory cell for one word, R
It requires more instruction cycles than the number of words of AM,
In the case of a typical one-chip microprocessor, tens to hundreds of instruction cycles are required, and there is a problem in that it takes a long time to initialize the RAM. Furthermore, during initialization, the central processing unit is occupied and a considerable portion of the program area is used for the initialization program. Therefore, an object of the present invention is to facilitate the initialization of memory cells.

[Means for solving problems]

The gist of the present invention is to have word line selection means for activating one of (k) word lines based on an address signal as well as simultaneous selection means for activating a plurality of word lines at the same time. In the read or write mode, one of the word lines is activated by an address signal, and data is read or written from the memory cell selected by the activated word line.However, When it is necessary to initialize memory cells, a simultaneous selection signal is supplied to activate multiple word lines.In this way, by activating multiple word lines, a large number of memory cells are simultaneously selected. By using the writing means, predetermined data can be simultaneously written into the selected memories, and the memory cells can be initialized in an extremely short time.

As a result, the exclusive time of the central processing unit is shortened, and the program area for holding the initialization program is also reduced. [Embodiment] FIG. 1 is a logic circuit diagram showing an embodiment of the present invention. In the figure, only the same reference numerals are given to the parts corresponding to the parts of the conventional example shown in FIG. 4, and the explanation thereof will be omitted. In this embodiment, the outputs Qo to Q3 of the address decoder 37 are
are connected to one input of the OR circuits 100 to 103, respectively, and a simultaneous selection signal 5ELECT can be supplied to the other input of the OR circuits 100 to 103. OR circuit 1o
.

The outputs of the AND circuits 17 to 103 are respectively supplied to one input of the AND circuits 17 to 20.
The precharge signal PG can be supplied to the other input as in the conventional case. Therefore, the outputs Qo to Q of the address decoder 37 are always supplied to the AND circuits F to 20 via the OR circuits 10075 to 103, and the simultaneous selection signal 5ELEC'l'' is simultaneously supplied to the OR circuits 100 to 103. Then, "1" is supplied to one input' of all the AND circuits 17 to 20. The address decoder 37 and AND circuits 17 to 20 collectively constitute word line selection means 110, and the OR circuits 1oo to 103 collectively constitute simultaneous 2@folding means 120. However, the memory cells 1 to 16 are connected to the memory cell array 130,
AND circuits 25 to 32 and inverters 33 to 36 and n
Channel yJOS transistor N l , 15 to N8
and constitute means 140 for inputting data as a whole.

Next, the operation will be explained with reference to the timing chart of FIG. It should be noted that normal data writing and data reading are the same as in the conventional example, so a description thereof will be omitted.

When initializing memory cells 1 to 16, when simultaneous selection signal 5ELECT is shifted to high level at time '11, OR circuits 100 to 103 output high level regardless of address signals AQ and Al. The signals are sent to AND circuits 17 to 20, respectively.

At time t, when the precharge signal PG reaches a high level l'74, all AND circuits F'? ! The outputs of r17 to r20 shift to high level, and the word lines WO to W3 become high level. As a result, the transfer gates T, , T2 of all memory cells 1 to 16 are turned on, and the storage nodes N, , N of each memory cell 1 to 16 are connected to the corresponding bit pairs BQ, BQ to B3 . It is electrically connected to B3.

Therefore, indeterminate data appears temporarily at the outputs 00 to 03 according to the memory states of the memory cells 1 to 16.

Therefore, if predetermined initialization data, for example (0, 1, 0, 1) is supplied to the inputs DO to D3, and the write signal WR is shifted to a high level at time t, 3, the AND circuit 26
, 27, 30, 31 become high level, and the n-channel MOS transistors N2tN3 . N5tN7 turns on, Nl, N4°N5. Ng remains off. Therefore, bit lines BO, Bl, B2 . B3 is grounded and memory cells 1°2.3, 4.9, 10, 11.1
2 has "0", 5, 6° 7.8, 13, 14, 15.
16 is simultaneously written with "1". therefore,
Word aW1 is selected by address signals AQ and Al from time t14 to tIs, and the outputs 00 to 03 are (
0,1,0,1> appears.

FIG. 3 is a logic circuit diagram showing another embodiment of the present invention,
This is an example in which memory cells to be initialized are selectively selected. That is, the simultaneous selection signal 5ELECT is the word awo, WI
Only the OR circuits 100 and 101 provided corresponding to K are supplied, and the inverter 10 is supplied to the AND circuits 19 and 20.
4, an inverted signal of the simultaneous selection signal 5ELECT is supplied. Therefore, memory cells 1, 2, 5, 6, 9
, 10.13.14 are initialized at the same time, but the remaining memory cells can hold data without being initialized.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention, FIG. M2 is a timing chart diagram of one embodiment, FIG. 3 is a logic circuit diagram of another embodiment, and FIG. 4 is a logic circuit diagram of a conventional example. 21 and FIG. 5 are timing charts of a conventional example. 110... Word line selection means, 120...
. . . simultaneous selection means, 130 . . . memory cell array, 140 . . . means for writing data.

Claims (1)

[Claims] a memory cell array consisting of a plurality of word lines and a plurality of memory cells selectable by the activated word lines;
In a storage device comprising means for writing data into a selected memory cell and a word line designation section for activating a word line, the word line designation section is configured to activate one of a plurality of word lines based on an address signal. A storage device comprising: word line selection means for activating a book; and simultaneous selection means for simultaneously activating a plurality of word lines based on a simultaneous selection signal.