JPS6318222B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a conditional branching method in a program control device controlled by a microprogram, etc., and in particular, it determines a plurality of conditions, and based on the results, determines a planned branch destination. This relates to a conditional branching method that branches to .

In general, a conditional branch instruction in a program control device is used to branch to each branch destination so that a predetermined processing program is activated depending on, for example, the positive, negative, or zero result of an operation, the state of a condition code, or the cause of an interrupt. . In such a conditional branch instruction, when branching to a planned branch destination after determining multiple conditions, the conventional method is to determine each condition serially.
Since processing time is required, and a situation may occur in which the previously determined condition changes during multiple condition determinations, it is not always possible to branch to a branch destination that matches each condition at the moment of branching. The problem was that it was not guaranteed.

Therefore, an object of the present invention is to make it possible to simultaneously determine multiple conditions with a simple configuration when determining multiple conditions and branching to a planned branch destination based on the determination results, thereby solving the aforementioned problems. The aim is to eliminate the

To this end, the present invention provides a program memory storing a program, an instruction register storing an instruction read from the program memory, and a conditional branch instruction when the instruction read to the instruction register is a conditional branch instruction. A program control device comprising a branch destination address register in which a branch destination address is set in order to modify at least a part of the branch destination address based on a plurality of external conditions and branch to a planned branch destination address. and the conditional branch instruction includes preset information that indicates that at least some of the plurality of conditions are deemed to have been met, and preset information that indicates that at least some of the plurality of conditions are deemed to have not been met. preset means storing mask information and presetting the plurality of conditions based on preset information in the conditional branch instruction; and a mask masking the plurality of conditions based on the mask information in the conditional branch instruction. means for determining a branch destination address according to conditions determined by the presetting means and the masking means when the instruction read from the program memory to the instruction register is a conditional branch instruction; The feature is that it is set in the branch destination address register.

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a flowchart for explaining a conventional conditional branching method, FIG. 2 is a flowchart for explaining a conditional branching method according to the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. .

Multiple conditions, e.g. “1” for A, B, C, D,
In the case of a branch instruction that judges “0” and branches to the planned branch destination, the conventional method is the first method.
As shown in the flowchart, first, condition A
, then condition B is determined, condition C is further determined, and finally condition D is determined, and based on the results, the process branches to the planned branch destination. Because multiple conditions are determined in series in this way, the processing time increases, and the previously determined conditions may change until all conditions have been determined. There is a problem in that there is no guarantee that a branch can be made to a branch destination that meets all the conditions at a certain moment.

FIG. 2 is a flowchart for explaining the branching method of the present invention, in which four conditions A, B, C, and D are simultaneously determined, and a branch is made to a scheduled branch destination depending on the combination of the respective determination results. Such simultaneous determination eliminates all the drawbacks of the conventional method described above.

FIG. 3 shows an embodiment of the branching method of the present invention, in which 1 is an instruction counter, 2 is a +1 circuit,
3 is a program memory, 4 is an instruction register, 5 is a branch address register, 6 is an OR gate circuit which is a preset means, 7 is an AND gate circuit which is a mask means, and 8 is a multiplexer circuit for selecting various condition groups. .

When processing normally proceeds sequentially, as is well known, the address of the program memory 3 is updated one after another by the instruction counter 1 and the +1 circuit 2, and instructions are sequentially read from the program memory and executed. When a conditional branch instruction is read, it branches to the planned branch destination as a result of the condition judgment, but this branch instruction is generally used during the instruction to specify the branch address to which the branch should be taken when the specified condition is met. is stored, and this is sent from the branch address register 5 to the instruction counter 1 so as to cause a branch to a predetermined address. JADD of instruction register 4 is this branch destination address area. PS is a preset designation area used by the present invention, MS is a mask designation area also used by the invention, S is a condition selection designation area, and J is a branch instruction designation area. Conditional branching according to the present invention is performed as follows.

That is, the branch destination address area has, for example, a 12-bit configuration, and is given as F, 0, and 3 (hexadecimal), and the four conditions, for example, A, B, C, and D are judged,
As a result, part of the branch address is modified with 4 bits given by hexadecimal 0, and the branch is branched to the planned branch destination. The four conditions A to D are selected by the multiplexer circuit 8 according to the specification of the condition selection specification area S. Here, for the sake of simplicity, an example will be described in which branch addresses are modified according to the "1" and "0" states of A, B, C, and D. Now, consider the case where the four selected conditions A to D are A=0, B=0, C=1, and D=1.

Assuming that the preset designated area PS is all "0" and the masked area MS is all "1" and no designation is made, the AND gate circuit 7 which is the masking means will not mask all of them, and conditions A~ D is output as is. Also, since there is no preset in the OR gate circuit 6 which is the presetting means and conditions A to D are output as they are, the 4 bits of the branch address register contain 0, 0, 1, 1.
is input, F, 3, 3 (hexadecimal) becomes a branch address and is stored in instruction counter 1, and the instruction at the branch destination address is executed.

Here, the functions of the preset means 6 and the mask means 7 will be explained. The preset means 6 is for presetting an arbitrary condition to "1" by instructing the preset designation area PS about the condition. For example, the above-mentioned condition A=0, B=
If you want to treat A as ``1'' regardless of whether 0, C=1, or D=1, specify ``1'' in the bit corresponding to A in the preset specification area PS, and you can use it as a preset means. The OR gate circuit 6 always outputs "1" for the bit under condition A, regardless of the state of A. Therefore, in this case, "1011" is finally input to the branch address register 5.

Further, the masking means 7 masks an arbitrary condition by instructing the mask designation area MS about the condition. For example, if you want to mask D regardless of the above conditions, if you specify "0" to the bit corresponding to D in the mask designation area MS, the AND gate circuit 7 that is the masking means will change to the state of D. The bit of condition D is always output as "0" regardless of the condition. Therefore, in this case, if no preset is specified, "0010" is input to the branch address register 5, and if the above-mentioned preset is also specified, "1010" is input to the branch address register 5. It will be done.

Note that the branch instruction specification J is always specified in a branch instruction, and this specification causes a gate signal G to be issued. This activates the gate for input to.

In this way, the preset means 6, the mask means 7,
This allows not only branching based on the judgment results of a plurality of conditions, but also masking and presetting by selecting arbitrary conditions.

As explained above, according to the present invention, a plurality of conditions are determined at the same time, and based on the results, each branch is branched to a scheduled branch destination.
It has the advantage of short processing time and is not affected by changes in conditions during the judgment process, which is the case with conventional methods that judge multiple conditions in series. The circuit means used can be easily constructed using well-known multiplexers, AND circuits, OR circuits, etc., and can provide an extremely effective branching system.

[Brief explanation of the drawing]

FIG. 1 is a flowchart for explaining a conventional conditional branching method, FIG. 2 is a flowchart for explaining a conditional branching method according to the present invention, and FIG. 3 is a diagram showing an embodiment of the present invention. . In the figure, 1 is an instruction counter, 2 is a +1 circuit, 3 is a program memory, 4 is an instruction register, 5 is a branch address register, 6 is an OR gate circuit which is a preset means, 7 is an AND gate circuit which is a mask means, and 8 is various types. This is a multiplexer circuit for selecting a group of conditions.

Claims (1)

[Scope of Claims] 1. A program memory in which a program is stored, an instruction register for storing instructions read from the program memory, and when the instruction read into the instruction register is a conditional branch instruction, an instruction from outside the instruction is provided. A program control device comprising: a branch destination address register in which a branch destination address is set; and, in the conditional branch instruction, preset information that assumes that at least some of the plurality of conditions are satisfied, and mask information that assumes that at least some of the plurality of conditions are not satisfied. are stored, and preset means for presetting the plurality of conditions based on preset information in the conditional branch instruction; and masking means for masking the plurality of conditions based on mask information in the conditional branch instruction. If the instruction read from the program memory to the instruction register is a conditional branch instruction,
determining a branch destination address according to conditions determined by the preset means and the mask means;
A conditional branch method in a program control device, characterized in that the branch destination address register is set.