JPS6318215Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a remote control lock circuit for a remote control device in a television receiver.

TV receivers that come with remote controls are equipped with a remote control lock circuit to prevent children from tampering with the remote control transmitter, but the locking and unlocking of this lock circuit can be done by installing a lock circuit on the TV receiver itself. This was done by operating a switch, and could not be controlled from the remote control transmitter side.

The purpose of the present invention is to enable the control of the remote control lock circuit on the main body side to be controlled by the remote control transmitter side.

The present invention will be explained below with reference to examples. In Fig. 1, 1 is a remote control transmitter, in which a pulse code is modulated to, for example, 42KHz by key operation, electrical-optical conversion is performed by a light emitting diode, and near-infrared light is emitted. The near-infrared light is received by a receiver 2 on the side of the television receiver body. This receiving section 2 includes a photodetector such as a phototransistor or photodiode that receives near-infrared light and converts it into an electrical signal, and a band amplification/detection device that amplifies the signal from the photodetector and further removes the 42KHz carrier wave. A serial-to-parallel converter section converts the serial pulse code from the band amplification/detection section into a parallel n-bit pulse code. The n-bit pulse code from the receiving section 2 passes through a remote control lock gate 3 consisting of AND gates ₃₁ to _3o via a parallel n-bit line 30, and then enters the main decoder 4.
The main decoder 4 decodes the code and outputs control signals for power on/off, channel switching, volume adjustment, etc.

The gate 3 opens when the Q output of the R/S flip-flop 5 is at the H level, and closes when the Q output is at the L level. level and also inverter 7
When the output of Q changes from L level to H level, it is reset and the Q output goes to L level. This inverter 7 is of a three-state type, and when the control terminal 7a is at L level, it inverts the input signal, but when it is at H level, the output is set at L level regardless of the input signal. This control terminal 7a is connected to the S input of the flip-flop 5, so that the inverter 7 can influence the flip-flop 5 only when the S input of the flip-flop 5 is at the low level. 8 is a momentary type lock switch for applying an L pulse to the input of the inverter 7. 9 to 11 are resistances.

12A to _12j are j lock release decoders each receiving a parallel n-bit output from the receiver 2 and decoding _a different code. ) to the input of the AND gate 13, and also to the second decoder 12
₂ is connected to another input of the AND gate 13 via a delay circuit 14 ₁ of time t ₁ that delays the output of the H level.
Hereinafter, the third to j-1 decoders operate at times t ₂ to t _j-2
and the last decoder 12 _j enters another input of the AND gate 13 via a delay circuit 14 _j-1 at time t _j-1 . The above circuit constitutes the first sub-decoder 31. In this case, delay circuit 1
4 ₁ ...14 The delay time t _{1 ...} t _j-1 of j-1 is t ₁ < ...
The length is determined to be <t _j-1 . The output of the AND gate 13 is applied to the S input of the flip-flop 5 and the control terminal 7a of the inverter 7.

15 ₁ to 15 _k are k remote control lock decoders that each receive a parallel n-bit output from the receiver 2 and decode a different code, and are different from the lock release decoders 12 ₁ to 12 _j described above. Decipher the ivy code. The first decoder 15 ₁ is directly connected to one input of the AND gate 16, and the second decoder 15 ₂ is connected to another input of the AND gate 16 through a delay circuit 17 ₁ of time t' ₁ which delays the output of the H level. In the following, the third to k-1th decoders are time
to each separate input of the AND gate 16 via a delay circuit from _{t' 2} to t' _k-2 , and the last decoder 15 _k to the AND gate via a delay circuit 17 _k-1 at time t' _k- 1. 16 separate inputs. The second sub-tecoder 32 is configured as described above. In this case, the delay time t' ₁ ... t' _k-1 of the delay circuits 17 ₁ ... 17 _k-1 is t' ₁
The length is determined to be <...<t′ _k-1 . The output of the AND gate 16 is applied to the R input of the flip-flop 5.

Figure 2 shows decoders 12 ₁ to 12 _j and 15 ₁ to 15 _k.
This is a specific circuit diagram of 2-input exclusive OR gates 18 ₁ to 18 _o , the number of which corresponds to the number n of parallel output bits from the receiver 2, and the gate 1.
an AND gate 19 receiving outputs of 8 ₁ to 18 _o ;
It is composed of n DIL switches 20 ₁ to 20 _o that set one code of the inputs of the gates 18 ₁ to 18 _o , and resistors 21 ₁ to 20 _o .

Next, the operation will be explained. Under normal conditions, both the R and S inputs of flip-flop 5 are at L level. And now the Q output is at H level,
Assume that AND gates 3 ₁ to 3 _o are open. Therefore, in order to lock the remote control on the television receiver side, it is sufficient to turn on the lock switch 8. As a result, the input of the inverter 7 becomes the L level, and since the control terminal 7a is also at the L level at this time, the output becomes the H level, and the R of the flip-flop 5 becomes the L level.
Participate in input. Therefore, the Q output becomes L level, AND gates ₃₁ to _3o are closed, and the remote control is locked. In other words, the code signal from the receiving section 2 cannot reach the main decoder 4. Next, in order to similarly release the remote control lock on the television receiver side, it is sufficient to press the lock release switch 6. As a result, the S input of flip-flop 5 becomes H level, the Q output becomes H level, and AND gate 3 ₁
~3 _o opens.

Next, in order to lock the remote control on the side of the remote control transmitter 1, codes corresponding to the different decoding codes of the decoders 15 ₁ , 15 _{2 .} 15
K・15 _K-1 ...Generate in the code order of 15 ₂ , 15 ₁ . In this case, by appropriately selecting the time of the delay circuits 17 ₁ to 17 _k-1 under the above conditions,
When the key operation on the remote control transmitter 1 of the code corresponding to the code of the last decoder 15 ₁ is completed and the output from that decoder 15 ₁ becomes H level, the output from the other delay circuits 17 ₁ to 17 _k be at H level at the same time, or have already become H level. This makes AND gate 1
All inputs of flip-flop 6 become H level, and an H level signal is outputted and input to the R input of flip-flop 5. Therefore, the Q output of flip-flop 5 becomes L level, AND gates ₃₁ to _3o are closed, and remote control locking is performed.

Next, to release the remote control lock on the similar remote control transmitter 1 side, decoders 12 ₁ , 12 ₂ . . .
12 _j , the codes corresponding to the different decoding codes are sent to the decoder 12 by key operations on the transmitter 1.
_j・12 _j-1 ...12 ₂・12 ₁ Codes are generated in this order. In this case, by appropriately selecting the time of the delay circuits 14 ₁ to 14 _j-1 under the above conditions,
When the key operation on the remote control transmitter 1 of the code corresponding to the code of the last decoder 12 ₁ is completed and the output from that decoder 12 ₁ becomes H level, the output from the other delay circuits 14 ₁ to 14 _j either become H level at the same time, or are already at H level. As a result, all the inputs of the AND gate 13 become H level,
An H level signal is output to the flip-flop 5.
Enter the S input of Therefore, the Q output of the flip-flop 5 becomes H level, and the AND gate 3
₁ to 3 _o open, the remote control lock is released, and the code signal from the receiver 2 is transmitted to the decoder 4.
, and you will be able to perform normal remote control operations.

The decoding codes of the decoders 12 ₁ to 12 _j and 15 ₁ to 15 _k are determined by the DIL switch 20 shown in FIG.
Since the code can be set as appropriate by turning on or off from ₁ to 20 _degrees , the user can freely set the code.

As described above, the present invention has a parallel n
A gate is inserted into the bit line, the gate is opened and closed by a latch, and the latch is controlled by the output of a sub-tecoder which inputs the signal of the parallel n bit lines, and the sub-tecoder is decoded. The gate can be opened and closed by generating a code by operating a key on a remote control transmitter. Therefore, it becomes possible to prevent the remote control transmitter from being tampered with.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a remote control lock circuit according to an embodiment of the present invention, and FIG. ₂ is a circuit diagram of a remote control lock circuit according to an _embodiment of the present invention.
5 ₁ to 15 _k is a specific circuit diagram. 4...Main decoder, 6...Lock release switch, 8...Lock switch, 30...Parallel n bit lines, 31/32...Subdecoder.

Claims (1)

[Claims for Utility Model Registration] (1) A gate inserted in the parallel n-bit line on the input side of the main decoder for decoding codes for power on/off, channel switching, etc., and a latch for opening and closing the gate; Parallel n on the input side of the gate
It consists of a sub-decoder which inputs the bit line signal and controls the latch by its output.By keying the decoding code of the sub-decoder with a remote control transmitter, the output from the sub-decoder becomes active. A remote control lock circuit for a television receiver, characterized in that: (2) Registration of a utility model characterized in that the sub-decoder includes a remote control lock decoder, and when the output from the remote control lock decoder becomes active, the gate is closed by the latch. A remote control lock circuit in a television receiver according to claim 1. (3) Registration of a utility model characterized in that the sub-decoder includes a lock release decoder, and when the output from the lock release decoder becomes active, the gate is opened by the latch circuit. A remote control lock circuit in a television receiver according to claim 1. (4) The sub-decoder is connected to two or more decoders,
Utility model registration claim 1 comprising a plurality of delay circuits that individually delay the outputs of the respective decoders by different times of zero seconds or more, and an AND gate that receives the outputs of the plurality of delay circuits. Remote control lock circuit in a television receiver. (5) The remote control lock circuit for a television receiver according to claim 1, wherein the sub-decoder includes a DIL switch for setting and changing a decoding code.