JPS63175457A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS63175457A JPS63175457A JP62005966A JP596687A JPS63175457A JP S63175457 A JPS63175457 A JP S63175457A JP 62005966 A JP62005966 A JP 62005966A JP 596687 A JP596687 A JP 596687A JP S63175457 A JPS63175457 A JP S63175457A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- thickness
- pellet
- film
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000011347 resin Substances 0.000 claims description 26
- 229920005989 resin Polymers 0.000 claims description 26
- 239000008188 pellet Substances 0.000 claims description 19
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、レジンモールド型半導体装置に関し、特に、
薄型面付パッケージの信頼性の向上をはかることができ
る技術に適用して有効な技術に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resin molded semiconductor device, and in particular,
The present invention relates to a technique that is effective when applied to a technique that can improve the reliability of thin surface-mounted packages.
従来のメモリ用大型ペレットを塔載したレジンモールド
型半導体装置や面付レジンモールド型半導体装置は、第
２図に示すように、タブ２の上にペレット１が塔載され
、このペレット１の電極（パッド）とリード３の内部リ
ード部３Ａとがワイヤ４で電気的に接続された後、レジ
ンでモールドされてパッケージ５としたものである。Ｉ
Ｃリードフレームについては１例えば、電子材料１９８
６年６月号、Ｐ、１３７〜Ｐ、１４２に記載がある。In conventional resin molded semiconductor devices and surface-mounted resin molded semiconductor devices in which large pellets for memory are mounted, a pellet 1 is mounted on a tab 2, and the electrodes of this pellet 1 are mounted on a tab 2, as shown in FIG. After the (pad) and the internal lead portion 3A of the lead 3 are electrically connected with the wire 4, the package 5 is molded with resin. I
1 for C lead frames, e.g. electronic materials 198
It is described in the June 6th issue, P, 137-P, 142.
しかしながら、前記従来のレジンモールド型半導体装置
では、３００ミル（ａｉｌ）のパッケージに。However, the conventional resin molded semiconductor device has a 300 mil (ail) package.
例えば、メモリ主力製品である４メガＤＲＡＭ（Ｄｙｎ
ａｍｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ
）の大型ペレット１を納める場合、タブ２が大きくなる
ため内部り−ド部３Ａの引き回わしが不可能となる。For example, 4 mega DRAM (Dyn
amic Random Access Memory
) When storing large pellets 1, the tab 2 becomes large, making it impossible to route the internal lead portion 3A.
また、例えば、面付レジンモールド型半導体装置の半田
リフロ一時における熱ストレスの影響によるパッケージ
クラック発生防止は、レジンモールドの厚さを厚くする
ことにより対応することができるが、近年、半導体装置
の薄型指向が強くなって来ているため、第２図に示すよ
うに、タブ２の下面とパッケージ５の裏面５Ａまでの厚
さＡが薄くなり、レジンクラックが発生するという問題
点を発明者が見い出した。Furthermore, for example, prevention of package cracks caused by thermal stress during solder reflow of surface-mounted resin molded semiconductor devices can be prevented by increasing the thickness of the resin mold. As the directionality has become stronger, the inventor discovered that the thickness A between the bottom surface of the tab 2 and the back surface 5A of the package 5 becomes thinner as shown in FIG. 2, causing resin cracks. Ta.
本発明の目的は、レジンモールド型半導体装置。The object of the present invention is to provide a resin mold type semiconductor device.
特に大型ペレットを搭載する半導体装置であっても、そ
のパッケージのレジンのクラック発生を防止することが
できる技術を提供することにある。In particular, it is an object of the present invention to provide a technique that can prevent cracks in the resin of a package of a semiconductor device mounted with a large pellet.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち１代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of one typical invention disclosed in this application is as follows.
すなわち、タブなしレジンモールド型半導体装置であっ
て、リードの内部リード部及びペレットをフィルムで支
持したものである。That is, it is a tabless resin molded semiconductor device in which the internal lead portions and pellets of the leads are supported by a film.
前記した手段によれば、タブをなくして、リードの内部
リード部及びペレットを薄いフィルムで支持したので、
タブの厚さから薄いフィルムの厚さを差引いた厚さだけ
ペレットから下のレジンモールドの厚さを厚くすること
ができるので、例えば１面付レジンモールド型半導体装
置の半田リフロ一時における熱ストレスの影響によるパ
ッケージクラックの発生を防止することができる。According to the above-mentioned means, since the tab is eliminated and the internal lead part of the lead and the pellet are supported by a thin film,
Since the thickness of the resin mold below the pellet can be increased by the thickness of the tab minus the thickness of the thin film, it is possible to increase the thickness of the resin mold below the pellet by the thickness of the tab. It is possible to prevent package cracks from occurring due to the impact.
以下、本発明の一実施例を図面を用いて具体的に説明す
る。Hereinafter, one embodiment of the present invention will be specifically described using the drawings.
なお、実施例を説明するための全回において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第１図は１本発明の一実施例のレジンモールド型半導体
装置の概略構成を示す断面図である。FIG. 1 is a sectional view showing the schematic structure of a resin molded semiconductor device according to an embodiment of the present invention.
本実施例のレジンモールド型半導体装置は、第１１ｉＷ
に示すように、厚さ２５〜５０μ厘の耐熱性フィルム１
０の上にリード３の内部リード部３Ａが熱圧着又は接着
剤で接着され、その後前記フィルム１０上にペレット１
が塔載され、このペレット１の電極（パッド）とリード
３の内部リード部３Ａとがワイヤ４で電気的に接続され
た後、レジンでモールドされてパッケージ５としたもの
である。The resin molded semiconductor device of this example has the 11th iW
As shown in the figure, a heat-resistant film 1 with a thickness of 25 to 50 μm
The internal lead portion 3A of the lead 3 is bonded onto the film 10 by thermocompression bonding or adhesive, and then the pellet 1 is bonded onto the film 10.
The electrode (pad) of the pellet 1 and the internal lead portion 3A of the lead 3 are electrically connected with a wire 4, and then molded with resin to form a package 5.
前記耐熱性フィルム１０の材料としては１例えばポリイ
ミド樹脂が用いられる。As the material for the heat-resistant film 10, for example, polyimide resin is used.
このようにタブをなくして、リード８の内部リード部３
Ａ及びペレット１を薄いフィルム１０で支持したので、
タブの厚さから薄いフィルムの厚さを差引いた厚さだけ
ペレットエから下のレジンモールドの厚さを厚くするこ
とができるので１例えば１面付レジンモールド型半導体
装置の半田リフロ一時における熱ストレスの影響による
パッケージクラックの発生を防止することができる。In this way, without the tab, the internal lead part 3 of lead 8
Since A and pellet 1 were supported by thin film 10,
Since the thickness of the resin mold below the pellet can be increased by the thickness of the tab minus the thickness of the thin film, it is possible to reduce heat stress during solder reflow of a one-sided resin mold type semiconductor device, for example. It is possible to prevent package cracks from occurring due to the impact.
これによりパッケージ５の全厚さを従来通りにしても、
ペレット１から下のレジンモールドの厚さマージンがと
れ、信頼性を確保することができる。As a result, even if the total thickness of package 5 is kept the same as before,
A thickness margin of the resin mold below the pellet 1 can be provided, and reliability can be ensured.
また、タブを用いていないので、内部リード部３Ａの引
き回わしが可能となる。Furthermore, since no tabs are used, the internal lead portion 3A can be routed.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
〔発明の効果〕
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.
タブなしレジンモールド型半導体装置であって、リード
の内部リード部及びペレットを薄いフィルムで支持した
ので、タブの厚さから薄いフィルムの厚さを差引いた厚
さだけペレットから下のレジンモールドの厚さを厚くす
ることができるので、例えば、面付レジンモールド型半
導体装置の半田リフロ一時における熱ストレスの影響に
よるパッケージクラックの発生を防止することができる
。This is a resin mold type semiconductor device without a tab, and the inner lead part of the lead and the pellet are supported by a thin film, so the thickness of the resin mold below the pellet is equal to the thickness of the tab minus the thickness of the thin film. Since the thickness can be increased, for example, it is possible to prevent package cracks from occurring due to the influence of thermal stress during solder reflow of a surface-mounted resin molded semiconductor device.
これによりパッケージの全厚さを従来通りにしても、ペ
レットから下のレジンモールドの厚さマージンがとれ、
信頼性を確保することができる。As a result, even if the total thickness of the package remains the same as before, there is still a margin for the thickness of the resin mold below the pellet.
Reliability can be ensured.
また、タブを用いないので、内部リード部３Ａの引き回
わしが可能となる。Furthermore, since no tabs are used, the internal lead portion 3A can be routed.
第１図は１本発明の一実施例のレジンモールド型半導体
装置の概略構成を示す断面図、第２図は、従来のレジン
モールド型半導体装置の問題点を説明するための図であ
る。
図中、■・・・ペレット、３・・・リード、３Ａ・・・
内部リード部、４・・・ワイヤ、５・・・パッケージ、
１０・・・耐熱性フィルムである。
第 １ 図
第 ２ 図
／θ−冊１ｋ・）すフイルムFIG. 1 is a sectional view showing a schematic configuration of a resin molded semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining problems with a conventional resin molded semiconductor device. In the figure, ■...pellet, 3...lead, 3A...
Internal lead part, 4... wire, 5... package,
10... Heat resistant film. Figure 1 Figure 2 / θ-book 1k・) film
Claims (1)
部リード及びペレットをフィルムで支持したことを特徴
とする半導体装置。 ２、前記フィルムが耐熱性であることを特徴とする特許
請求の範囲第１項に記載の半導体装置。 ３、前記耐熱性フィルムは、ポリイミド樹脂からなるこ
とを特許請求の範囲第１項又は第２項に記載の半導体装
置。 ４、前記フィルムの厚さが０．０２５ｍｍ〜０．０５０
ｍｍであることを特徴とする特許請求の範囲第１項乃至
第３項の各項に記載の半導体装置。 ５、前記半導体装置は、面付型半導体装置であることを
特徴とする特許請求の範囲第１項乃至第４項の各項に記
載の半導体装置。[Scope of Claims] 1. A resin molded semiconductor device without tabs, characterized in that an internal lead and a pellet are supported by a film. 2. The semiconductor device according to claim 1, wherein the film is heat resistant. 3. The semiconductor device according to claim 1 or 2, wherein the heat-resistant film is made of polyimide resin. 4. The thickness of the film is 0.025 mm to 0.050 mm.
The semiconductor device according to any one of claims 1 to 3, characterized in that the diameter is mm. 5. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a surface-mounted semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62005966A JPS63175457A (en) | 1987-01-16 | 1987-01-16 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62005966A JPS63175457A (en) | 1987-01-16 | 1987-01-16 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63175457A true JPS63175457A (en) | 1988-07-19 |
Family
ID=11625614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62005966A Pending JPS63175457A (en) | 1987-01-16 | 1987-01-16 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63175457A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0433695A3 (en) * | 1989-12-22 | 1991-10-02 | Texas Instruments Incorporated | Integrated circuit device and method to prevent cracking during surface mount |
| US5895969A (en) * | 1992-05-25 | 1999-04-20 | Hitachi, Ltd. And Hitachi Vlsi Engineering Corp. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| CN102655133A (en) * | 2011-03-04 | 2012-09-05 | 三星半导体(中国)研究开发有限公司 | Chip packaging component and manufacturing method for same |
-
1987
- 1987-01-16 JP JP62005966A patent/JPS63175457A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0433695A3 (en) * | 1989-12-22 | 1991-10-02 | Texas Instruments Incorporated | Integrated circuit device and method to prevent cracking during surface mount |
| US5895969A (en) * | 1992-05-25 | 1999-04-20 | Hitachi, Ltd. And Hitachi Vlsi Engineering Corp. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| CN102655133A (en) * | 2011-03-04 | 2012-09-05 | 三星半导体(中国)研究开发有限公司 | Chip packaging component and manufacturing method for same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0179803B1 (en) | Lead Exposure Semiconductor Package | |
| JPH05109975A (en) | Resin-sealed type semiconductor device | |
| JP2002110898A (en) | Semiconductor device | |
| JPH0777258B2 (en) | Semiconductor device | |
| JPS60167454A (en) | semiconductor equipment | |
| JPS63175457A (en) | semiconductor equipment | |
| JPH0546098B2 (en) | ||
| JPH01137660A (en) | semiconductor equipment | |
| JPS60120543A (en) | Semiconductor devices and lead frames used therein | |
| JP2852112B2 (en) | Semiconductor integrated circuit device | |
| JPH0357248A (en) | Resin-sealed semiconductor device using tape carrier method | |
| JP2971594B2 (en) | Semiconductor integrated circuit device | |
| KR100340862B1 (en) | Stack package and its manufacturing method | |
| JPS63152161A (en) | semiconductor equipment | |
| JPS59117250A (en) | Semiconductor device | |
| JP2968769B2 (en) | Resin-sealed semiconductor device | |
| JP3169072B2 (en) | Semiconductor device | |
| JP2732731B2 (en) | Lead frame, semiconductor device using the same, and method of manufacturing the same | |
| JPS59208767A (en) | semiconductor equipment | |
| JPH0485836A (en) | Semiconductor device | |
| JP2624212B2 (en) | TAB tape | |
| KR940010298A (en) | Semiconductor package and manufacturing method thereof | |
| JP2002100719A (en) | Resin-sealed semiconductor device | |
| JPH04278548A (en) | Resin sealed semiconductor device | |
| JPH03231435A (en) | Semiconductor integrated circuit device |