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JPS63175446A - Manufacturing method of bump type electrode - Google Patents

Manufacturing method of bump type electrode

Info

Publication number
JPS63175446A
JPS63175446A JP62007531A JP753187A JPS63175446A JP S63175446 A JPS63175446 A JP S63175446A JP 62007531 A JP62007531 A JP 62007531A JP 753187 A JP753187 A JP 753187A JP S63175446 A JPS63175446 A JP S63175446A
Authority
JP
Japan
Prior art keywords
bump
manufacturing
opening
photoresist
type electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62007531A
Other languages
Japanese (ja)
Inventor
Hiroaki Murakami
裕昭 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62007531A priority Critical patent/JPS63175446A/en
Publication of JPS63175446A publication Critical patent/JPS63175446A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 ・ 本発明は、半導体装置のバンプ型電極の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] - The present invention relates to a method for manufacturing bump-type electrodes for semiconductor devices.

〔発明の概要〕[Summary of the invention]

本発明け、半導体装置のバンプ型電極において7オトリ
ソダラフイーエ程、メジ千工程をくり返すことにより、
横方向の広がりの/bさく、また。
According to the present invention, by repeating the process for 700 degrees and 1000 times in bump type electrodes of semiconductor devices,
/b of the lateral extent, also.

異なった金属を数層に重ねることh;できるバンプ型電
極の製造方法である。
This is a method for manufacturing bump-type electrodes that allows several layers of different metals to be stacked.

〔従来の技術〕[Conventional technology]

従来、半導体装置のバンブ型WL極の構造及び製造方法
に関しては、数多くの提案がなされ、改良が加えられて
いる。
Conventionally, many proposals have been made and improvements have been made regarding the structure and manufacturing method of bump-type WL poles of semiconductor devices.

例えば、5otidstate tecnnotogy
 、 Aprit 1980年版の様に、フォトレジス
トを使用した場合、第2図にあるように、基板表面に金
嘴薄膜を形成しフォトレジストを塗布し、[極パッド上
部の開口部を形成して、メジ千をする工程からなり、こ
の場合・、大きなキノコ状のバッグb1形成されるもの
であっ几。
For example, 5otidstate technology
If a photoresist is used, as in the 1980 version of Aprit, as shown in Figure 2, a gold beak thin film is formed on the substrate surface and the photoresist is applied. It consists of a process of mulching, and in this case, a large mushroom-shaped bag is formed.

〔発明h″−−解決うとする問題点〕[Invention h″--problem to be solved]

しかし、前述の従来の技術は、フォトリソグラフィ一工
程が1回しか行なわれていない。そのため、メッキは上
方向に成長すると共に、横方向にも同様に成長するため
、首部に対して上部が不要に横方向に大きいといった不
安定な構造となっていた。そのため、バンプ型電極の微
細化ができないばかりか、実装不安定さが大きな問題と
なってい友。
However, in the conventional technique described above, one photolithography process is performed only once. Therefore, the plating grows upward and also in the lateral direction, resulting in an unstable structure in which the upper part is unnecessarily large in the lateral direction with respect to the neck. For this reason, not only is it impossible to miniaturize bump-type electrodes, but also mounting instability is a major problem.

本発明は、このような問題を解決するもので、その目的
とするところは、フォトリソグラフィーとメツ千工穆を
くり返し行なうことにより1首部に対して、横方向の広
がりの小さいバンプを形成し、バンプ型電極の微細化や
、実装安定性を得ようとするところくある。さらに、数
回性なうメツ。
The present invention is intended to solve such problems, and its purpose is to form a bump with a small width in the lateral direction on one neck by repeating photolithography and grooving. There are efforts to miniaturize bump-type electrodes and improve mounting stability. In addition, I had sex several times.

キ行程では、異なった金属を使うことができ、実装方式
の都合により、金層を組み合わせることのできる製造方
法でもある。
In the Q process, different metals can be used, and depending on the mounting method, it is also a manufacturing method that can combine gold layers.

〔問題点を解決するための手段〕[Means for solving problems]

半導体装置の電極パッド上に、バンプ型電極を一形成す
る製造方法にお込て。
The manufacturing method involves forming a bump-type electrode on the electrode pad of a semiconductor device.

(1)  基板表面に金属薄膜を形成する工程(2) 
 フォトレジストを塗布して、電極パッド上部に開口部
を形成する工1 (3)前記開口部に、メッキをしてバンプを形成する工
程 (4)  フォトレジストを塗布して、前記バンプの上
部に開i部を形成する工程 (5)  前記第゛2の開口部に、(3)と同じ金属ま
たは異なる金属なメツそしてバッグを形成する工程(6
)  前記(4) (5)をくり返す工程(7)フォト
レジストを剥離する工程 (8)  前記、金属薄膜をエツチングする工程からな
ることを特徴とする。バンプ型電極の製造方法。
(1) Step of forming a metal thin film on the substrate surface (2)
Step 1 of applying photoresist to form an opening above the electrode pad (3) Step of plating the opening to form a bump (4) Applying photoresist and forming an opening above the bump. Step (5) of forming an opening I. Step (6) of forming a bag made of the same metal or a different metal as in (3) in the second opening.
) The process of repeating (4) and (5) above (7) The process of peeling off the photoresist (8) The process of etching the metal thin film. Method for manufacturing bump-type electrodes.

〔実施例〕〔Example〕

以下に、本発明について、実施例に基づき詳細に説明を
する。
The present invention will be described in detail below based on examples.

まず、第1図にあるように、基板表面にクロム。First, as shown in Figure 1, chromium is applied to the surface of the substrate.

金からなる金属薄膜層205を形成し、フォトレジスト
206により、電甑パヅト@205上をのぞいてマスク
をする。次に、バンプとなる部分209を金メツ−?−
する。再びフォトレジスト207忙より、バンプ209
上部をのぞいてマスクする。この上にバンプとなる部分
210を鋼メッキする。°阿び7オトレジスト208に
より、バンプ210上部をのぞいてマスクする。この上
にバッグとなる部分211を金メツf−jる。この様に
、フォトリソグラフィー、メヴ千工糧をくり返すほど、
バンプはさらに高く形成される。
A metal thin film layer 205 made of gold is formed, and a photoresist 206 is used to mask the area except for the top of the electric oven pad @205. Next, place the part 209 that will become the bump with gold or gold. −
do. Bump 209 from photoresist 207 again
Peek at the top and mask. On top of this, a portion 210 that will become a bump is plated with steel. The upper part of the bump 210 is masked with the Abi7 photoresist 208. The part 211 that will become the bag is attached on top of this. In this way, the more I repeat the photolithography process,
The bumps are formed even higher.

最後に、フォトレジスト206 、 207 、 20
8を剥離し比後、金、クロム薄膜層205をエツチング
しバンプ型電翫製造工専は終了する。
Finally, photoresists 206, 207, 20
After removing 8, the gold and chromium thin film layer 205 is etched, and the bump type electric wire manufacturing process is completed.

以上の工程を経て、でき上がっ九本発明バンプ型電極は
、従来のバンプ型電極の製造方法に比べると、フォトリ
ソグラフィーとメー/=?工程をくり返しているので、
バンプ高さに対して横一方向の広がりの小さb構造を形
成することができる。
Through the above steps, the bump-type electrode of the present invention is completed.Compared to the conventional manufacturing method of bump-type electrodes, it is possible to produce a bump-type electrode using photolithography. Since the process is repeated,
A small b structure extending in one direction laterally with respect to the bump height can be formed.

本発明は、クロム、金を下地とじtが、チタン。In the present invention, chromium and gold are used as the base material, but titanium is used as the base material.

白金、ニッケルなどを使用したり、バンプとしてもニッ
ケル、鉛、スズ、半田などのすべての種類のバンプ型電
極に広く応用することhZ可能である。
It can be widely applied to all types of bump-type electrodes using platinum, nickel, etc., or using nickel, lead, tin, solder, etc. as bumps.

〔発明の効果〕〔Effect of the invention〕

本発明は、フォトリングラフイーと79キ工程をくり返
すことによって、従来の方法に比べ、パンク高さが同じ
場合には、パップ巾を半分程度にすることができる。こ
の几め、半導体装置の多電甑化、チップサイズの低減、
高密度実装などが可能となっt0バンブ形伏も安定化し
たために、密着強度が向上し、半導体装置、実装の信頼
性も向・止した。
In the present invention, by repeating the photophosphorography and 79-ki steps, the pap width can be approximately halved compared to the conventional method when the puncture height is the same. This method allows semiconductor devices to have multiple electric currents, reduces chip size,
High-density packaging has become possible and the t0 bump shape has become more stable, which has improved adhesion strength and improved the reliability of semiconductor devices and packaging.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は1本発明の実施例によるバンプ型電極製造工程
の断面図。 第2図は、従来のバンプ型電極製造工程の断面図。 101・・・・・・シリコン基板 102・?・・・・シリコン酸化膜 103・・・・・・アルミ電極パッド 104・・・・・・バヴシベーション膜105・・・・
・・クロム、 金薄5 106・・・・・・フォトレジスト 107・・・・・・金バンプ 201・・・・・・シリコン基板 202・・・・・・シリコン酸化膜 203・・・・・・アルミ電極パッド 204・・・…バッジベージリン膜 205・・・・・・クロム、 4[11に206・・書
…フォトレジスト 207・・・・・・フォトレジスト 208・・・…フォトレジスト 209・・・・・・金バンプ 210・・・・・・鋼バンプ
FIG. 1 is a cross-sectional view of a bump-type electrode manufacturing process according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional bump-type electrode manufacturing process. 101...Silicon substrate 102.? ... Silicon oxide film 103 ... Aluminum electrode pad 104 ... Bavscivation film 105 ...
...Chromium, gold thin 5 106...Photoresist 107...Gold bump 201...Silicon substrate 202...Silicon oxide film 203...・Aluminum electrode pad 204...Budge phosphorus film 205...Chromium, 4 [206 on 11...Write...Photoresist 207...Photoresist 208...Photoresist 209 ...Gold bump 210...Steel bump

Claims (1)

【特許請求の範囲】 集積回路の電極パッド上に、バンプ型電極を製造する方
法において、 (1)基板表面に金属薄膜を形成する工程 (2)フォトレジストを塗布し、電極パッド上部の開口
部を形成する工程 (3)前記開口部に金属をメッキして、バンプを形成す
る工程 (4)フォトレジストを塗布し、前記バンプの中央部の
開口部を形成する工程 (5)前記第2の開口部に、前記(3)と同じ金属また
は異なった金属をメッキして、バンプを形成する工程 (6)前記(4)(5)をくり返す工程 (7)レジストを剥離する工程 (8)前記金属薄膜をエッチングする工程からなること
を特徴とするバンプ型電極の製造方法
[Claims] A method for manufacturing bump-type electrodes on electrode pads of integrated circuits, which includes: (1) forming a metal thin film on the substrate surface; (2) applying photoresist to form an opening above the electrode pad; (3) Step of plating the opening with metal to form a bump. (4) Applying photoresist to form an opening in the center of the bump. (5) Step of forming a bump at the center of the second A step of plating the opening with the same metal or a different metal as in (3) above to form a bump (6) A step of repeating (4) and (5) above (7) A step of peeling off the resist (8) A method for manufacturing a bump-type electrode, comprising the step of etching the metal thin film.
JP62007531A 1987-01-16 1987-01-16 Manufacturing method of bump type electrode Pending JPS63175446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62007531A JPS63175446A (en) 1987-01-16 1987-01-16 Manufacturing method of bump type electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62007531A JPS63175446A (en) 1987-01-16 1987-01-16 Manufacturing method of bump type electrode

Publications (1)

Publication Number Publication Date
JPS63175446A true JPS63175446A (en) 1988-07-19

Family

ID=11668364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62007531A Pending JPS63175446A (en) 1987-01-16 1987-01-16 Manufacturing method of bump type electrode

Country Status (1)

Country Link
JP (1) JPS63175446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323535A (en) * 1991-02-25 1994-06-28 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323535A (en) * 1991-02-25 1994-06-28 Canon Kabushiki Kaisha Electrical connecting member and method of manufacturing the same

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