JPS63174348A - Stacked structure semiconductor device - Google Patents
Stacked structure semiconductor deviceInfo
- Publication number
- JPS63174348A JPS63174348A JP62005071A JP507187A JPS63174348A JP S63174348 A JPS63174348 A JP S63174348A JP 62005071 A JP62005071 A JP 62005071A JP 507187 A JP507187 A JP 507187A JP S63174348 A JPS63174348 A JP S63174348A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- semiconductor device
- layer element
- stacked structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims description 51
- 239000011229 interlayer Substances 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
Landscapes
- Local Oxidation Of Silicon (AREA)
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、積層構造を有する半導体装置に係わり、特に
層間絶縁膜の改良をはかった積層構造半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device having a stacked structure, and particularly to a stacked structure semiconductor device with an improved interlayer insulating film.
（従来の技術）
従来、半導体素子の集積度を上げるために、素子の微細
化が進められているが、近年この素子の微細化も限界に
近くなっている。そこで最近、素子を積層化することに
よって集積度を向上させた、いわゆる積層構造半導体装
置（３次元ＩＣ）が提案されている。(Prior Art) Conventionally, in order to increase the degree of integration of semiconductor devices, miniaturization of semiconductor devices has been progressing, but in recent years, miniaturization of these devices has also reached its limit. Therefore, recently, a so-called stacked structure semiconductor device (three-dimensional IC) has been proposed in which the degree of integration is improved by stacking elements.
３次元ＩＣを製造するには、まず第３図（ａ）に示す如
＜Ｓｉ基板１０上に下層素子２０を形成し、この上に層
間絶縁膜３０となる５ｉ０２膜をＣＶＤ法で堆積する。To manufacture a three-dimensional IC, first, as shown in FIG. 3(a), a lower layer element 20 is formed on a Si substrate 10, and a 5i02 film, which will become an interlayer insulating film 30, is deposited thereon by the CVD method.
さらに、この上に上層素子の基板となる多結晶ＳＬ膜４
０及びキャップ層４１となる５ｉ０２膜を順次堆積する
。この状態で、周知のビームアニール法により多結晶Ｓ
ｔ膜４０を単結晶化しキャップ層４１を剥離する。次い
で、第３図（ｂ）に示す如く、周知の選択酸化法により
素子分離を行い、その後上層素子を形成する。これによ
り、下層素子と上層素子とが層間絶縁膜を挟んで積層さ
れた３次元ＩＣが形成されることになる。なお、図中２
１はゲート電極、２４は金属配線、４０′はＳｉの単結
晶層、４３はＳｉＮ膜、４４は素子分離用酸化膜を示し
ている。Furthermore, on top of this, a polycrystalline SL film 4 that will become the substrate of the upper layer element.
0 and 5i02 films that will become the cap layer 41 are sequentially deposited. In this state, polycrystalline S
The t film 40 is made into a single crystal, and the cap layer 41 is peeled off. Next, as shown in FIG. 3(b), element isolation is performed by a well-known selective oxidation method, and then upper layer elements are formed. As a result, a three-dimensional IC is formed in which a lower layer element and an upper layer element are stacked with an interlayer insulating film in between. In addition, 2 in the figure
1 is a gate electrode, 24 is a metal wiring, 40' is a Si single crystal layer, 43 is a SiN film, and 44 is an oxide film for element isolation.
しかしながら、この種の装置にあっては次のような問題
があった。即ち、前記第３図（ｂ）に示す如く、Ｓｔ単
結晶層４０′の酸化工程において、酸化剤は酸化される
べき領域の表面から基板内部に拡散し５ｉ０２膜を形成
する。このとき、層間絶縁膜３０を形成するＣＶＤ−５
ｉ０２膜では、”ある。そして、ゲート電極２１或いは
配線２４の酸化は、素子特性を低下させる大きな要因と
なる。However, this type of device has the following problems. That is, as shown in FIG. 3(b), in the step of oxidizing the St single crystal layer 40', the oxidizing agent diffuses into the substrate from the surface of the region to be oxidized to form a 5i02 film. At this time, CVD-5 forming the interlayer insulating film 30
In the case of the i02 film, oxidation of the gate electrode 21 or the wiring 24 becomes a major factor in degrading device characteristics.
（発明が解決しよ゛うとする問題点）
このように従来の３次元ＩＣでは、素子分離のための酸
化工程において下層素子のゲート電極や配線層等が酸化
されてしまい、これに起因して素子特性が劣化する等の
問題があった。(Problems to be Solved by the Invention) As described above, in conventional three-dimensional ICs, the gate electrodes, wiring layers, etc. of lower layer elements are oxidized during the oxidation process for element isolation, and this causes problems. There were problems such as deterioration of device characteristics.
本発明は上記事情を考慮してなされたもので、その目的
とするところは、上層の酸化工程により下層素子のゲー
ト電極や配線等が酸化されるのを防止することができ、
素子特性の向上をはかり得る積層構造半導体装置を提供
することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to prevent the gate electrodes, wiring, etc. of the lower layer element from being oxidized by the oxidation process of the upper layer.
An object of the present invention is to provide a stacked structure semiconductor device that can improve device characteristics.
［発明の構成］
（問題点を解決するための手段）
本発明の骨子は、層間・絶縁膜の改良により、下層素子
のゲート電極や配線等の酸化を防止することにある。[Structure of the Invention] (Means for Solving Problems) The gist of the present invention is to prevent oxidation of gate electrodes, wiring, etc. of lower layer elements by improving interlayer/insulating films.
即ち本発明は、下層素子上に層間絶縁膜を介して上層素
子を形成した積層構造半導体装置において、前記層間絶
縁膜を、シリコン酸化膜からなる第１絶縁膜と、この第
１絶縁膜より酸素に対する拡散係数の低い物質であり、
上記第１絶縁膜中或いは該絶縁膜と前記下層素子との間
に配置された上記構成であれば、上層の酸化工程におけ
る酸化剤の拡散が第２絶縁膜により抑えられ、下層素子
への酸化剤の拡散を抑制することができる。That is, the present invention provides a stacked structure semiconductor device in which an upper layer element is formed on a lower layer element via an interlayer insulating film, in which the interlayer insulating film is a first insulating film made of a silicon oxide film, and oxygen is removed from the first insulating film. It is a substance with a low diffusion coefficient for
With the above structure disposed in the first insulating film or between the insulating film and the lower layer element, the second insulating film suppresses the diffusion of the oxidant in the oxidation process of the upper layer, and prevents oxidation to the lower layer element. Diffusion of the agent can be suppressed.
従って、下層素子を酸化から保護することが可能となる
。Therefore, it is possible to protect the underlying elements from oxidation.
（実施例）
以下、本発明の詳細を、図示の実施例によって説明する
。(Example) Hereinafter, the details of the present invention will be explained by referring to the illustrated example.
第１図は本発明の一実施例に係わる３次元ＩＣの概略構
成を示す断面図である。図中１０はＳｉ基板であり、こ
の基板１０上には、ゲート電極２１、ソース・ドレイン
領域２２ａ、２２ｂ。FIG. 1 is a sectional view showing a schematic configuration of a three-dimensional IC according to an embodiment of the present invention. In the figure, 10 is a Si substrate, and on this substrate 10 are a gate electrode 21 and source/drain regions 22a, 22b.
５ｉ０２膜２３及びＡ１配線層２４等からなるＭＯＳト
ランジスタ（下層素子）２０が形成されている。下層素
子２０上には５ｉ０２膜（第１絶縁膜）３１．ＳｉＮ膜
（第２絶縁膜）３２及び５ｉ０２膜（第１絶縁膜）３３
からなる層間絶縁膜３０が堆積され、その上には単結晶
Ｓｉ層４０′及び素子分離用酸化膜４４が形成され、単
結晶Ｓｉ層４０′にはゲート電極５１及びソース・ドレ
イン領域５２ａ、５２ｂ等からなるＭＯＳトランジスタ
（上層素子）５０が形成されている。A MOS transistor (lower layer element) 20 is formed of a 5i02 film 23, an A1 wiring layer 24, and the like. On the lower layer element 20 is a 5i02 film (first insulating film) 31. SiN film (second insulating film) 32 and 5i02 film (first insulating film) 33
An interlayer insulating film 30 is deposited, and a single-crystal Si layer 40' and an oxide film 44 for element isolation are formed thereon, and a gate electrode 51 and source/drain regions 52a, 52b are formed on the single-crystal Si layer 40'. A MOS transistor (upper layer element) 50 is formed.
１０上にＭＯＳトランジスタ等の上層素子２０を形成し
、その上に層間絶縁膜としての５ｉ０２膜３１を５００
０ ［人］の厚さに堆積する。ここまでは、従来一般的
な製造工程と同様である。An upper layer element 20 such as a MOS transistor is formed on 10, and a 5i02 film 31 as an interlayer insulating film is formed on top of the upper layer element 20, such as a MOS transistor.
0 Deposits to the thickness of [person]. The steps up to this point are similar to conventional manufacturing processes.
次いで、第２図（ｂ）′に示す如く、５ｉ０２膜３１上
に厚さ１０００ ［人］のＳｉＮ膜（第２絶縁膜）３２
及び厚す５０００ ［人］のＳｉｏ２膜（第１絶縁膜）
３３を堆積する。つまり、層間絶縁膜３０としてＳ ｉ
０２ ／Ｓ ｉＮ／Ｓ ｉ０２の３層構造膜を形成する
。続いて、層間絶縁膜３０上に厚さＢｏｏｏ［人］の多
結晶Ｓｉ膜４０及びキャップ層４１としての厚さ４００
０ ［人］の５ｉ０２膜を堆積する。Next, as shown in FIG. 2(b)', a SiN film (second insulating film) 32 with a thickness of 1000 [people] is formed on the 5i02 film 31.
and Sio2 film (first insulating film) with a thickness of 5000 [people]
Deposit 33. In other words, as the interlayer insulating film 30, S i
A three-layer structure film of 02/S iN/S i02 is formed. Subsequently, a polycrystalline Si film 40 with a thickness of Boooo [people] and a thickness of 400mm as a cap layer 41 are formed on the interlayer insulating film 30.
Deposit 5i02 film of 0 [person].
次いで、第２図（ｃ）に示す如く、周知の電子ビームア
ニールにより多結晶Ｓｉ膜４０を単結晶化し、キャップ
層４１を剥離する。次いで、第２図（ｄ）に示す如く、
単結晶化したＳｉ層４り′上に５ｉ０２膜４２及びＳｉ
Ｎ膜４３を堆積し、素子形成領域以外のＳｉＮ膜４３を
除去する。Next, as shown in FIG. 2(c), the polycrystalline Si film 40 is made into a single crystal by well-known electron beam annealing, and the cap layer 41 is peeled off. Next, as shown in FIG. 2(d),
5i02 film 42 and Si
A N film 43 is deposited, and the SiN film 43 outside the element formation region is removed.
次いで、第２図（ｅ）に示す如＜ 、１０００ ［”Ｃ
１の水素燃焼酸化により、非能動領域のＳｔを全て酸こ
れ以降は、ＳｉＮ膜４３を除去した後、前記第１図に示
す如くゲート電極５１及びソース・ドレイン領域５２ａ
、５２ｂ等を形成することによって、上層素子５０が形
成される。つまり、層間絶縁膜３０を挟んで下層素子且
及び上層素子５０が積層されることになる。Next, as shown in FIG. 2(e), 1000["C
After that, after removing the SiN film 43, the gate electrode 51 and source/drain regions 52a are removed as shown in FIG.
, 52b, etc., the upper layer element 50 is formed. In other words, the lower layer element and the upper layer element 50 are stacked with the interlayer insulating film 30 in between.
かくして形成された３次元ＩＣは、下層素子２０のゲー
ト電極２１や配線層２４等が酸化されることがなく、下
層素子２０も良好な素子特性を示した。また、層間絶縁
膜３０におけるＳｉＮ膜３２は５ｉ０２ Ｂ１．３２で
覆われているので、ビームアニール中に窒素が再結晶Ｓ
ｉ層中に拡散することはない。従って、Ｓｉ中にＮが拡
散してＳｉ／５ｉ０２の界面において多くの界面準位が
発生する等の不都合もない。また、高温、長時間の酸化
工程を任意に取入れることができるので、素子分離特性
を向上させることもできる。従って、３次元ＩＣの素子
特性の向上をはかり得、その有用性は絶大である。In the three-dimensional IC thus formed, the gate electrode 21, wiring layer 24, etc. of the lower layer element 20 were not oxidized, and the lower layer element 20 also exhibited good device characteristics. In addition, since the SiN film 32 in the interlayer insulating film 30 is covered with 5i02 B1.32, nitrogen is recrystallized S during beam annealing.
It does not diffuse into the i-layer. Therefore, there is no problem such as N being diffused into Si and many interface states being generated at the Si/5i02 interface. Furthermore, since a high temperature, long time oxidation process can be optionally employed, element isolation characteristics can also be improved. Therefore, it is possible to improve the element characteristics of a three-dimensional IC, and its usefulness is enormous.
なお、本発明は上述した実施例に限定されるも下層素子
との間にＳｉＮ等の第２絶縁膜を配置したものであれば
よい。また、第２絶縁膜はＳｉＮ膜に限るものではなく
、３ ｉ ０２膜よりも酸素に対する拡散係数の低い絶
縁膜であればよい。その他、本発明の要旨を逸脱しない
範囲で、種々変形して実施することができる。It should be noted that the present invention is not limited to the above-described embodiments, but may be one in which a second insulating film such as SiN is disposed between the lower layer element and the second insulating film. Furthermore, the second insulating film is not limited to the SiN film, and may be any insulating film that has a lower diffusion coefficient for oxygen than the 3i02 film. In addition, various modifications can be made without departing from the gist of the present invention.
［発明の効果］
以上詳述したように本発明によれば、上下素子を分離す
る層間絶縁膜を５ｉ０２からなる第１絶縁膜とＳｉＮ等
からなる第２絶縁膜との２層若しくは３層構造としてい
るので、上層の酸化工程における下層素子の酸化を未然
に防止することができ、これにより素子特性の向上をは
かり得る。[Effects of the Invention] As detailed above, according to the present invention, the interlayer insulating film separating the upper and lower elements has a two-layer or three-layer structure of a first insulating film made of 5i02 and a second insulating film made of SiN or the like. Therefore, oxidation of the lower layer element during the oxidation process of the upper layer can be prevented, thereby improving the element characteristics.
第１図は本発明の一実施例に係わる３次元ＩＣの概略構
成を示す断面図、第２図は上記３次元ＩＣの製造工程を
示す断面図、第３図は従来の３次元ＩＣの問題点を説明
するための断面図である。
１０・・・Ｓｉ基板、２０・・・下層素子、２１・・・
デー１絶縁膜）、４０・・・多結晶Ｓｉ膜、４０′・・
・単結晶Ｓｔ層、４１・・・キャップ層、４３・・・Ｓ
ｉＮ膜、５０・・・上層素子。FIG. 1 is a sectional view showing a schematic configuration of a three-dimensional IC according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the three-dimensional IC, and FIG. 3 is a problem with the conventional three-dimensional IC. FIG. 3 is a cross-sectional view for explaining the points. DESCRIPTION OF SYMBOLS 10... Si substrate, 20... Lower layer element, 21...
Day 1 insulating film), 40...polycrystalline Si film, 40'...
- Single crystal St layer, 41... cap layer, 43... S
iN film, 50...upper layer element.
Claims (3)
した積層構造半導体装置において、前記層間絶縁膜は、
シリコン酸化膜である第１絶縁膜と、この第１絶縁膜よ
り酸素に対する拡散係数の低い物質であり、上記第１絶
縁膜中或いは該絶縁膜と前記下層素子との間に配置され
た第２絶縁膜とからなるものであることを特徴とする積
層構造半導体装置。(1) In a stacked structure semiconductor device in which an upper layer element is formed on a lower layer element via an interlayer insulating film, the interlayer insulating film is
a first insulating film, which is a silicon oxide film; and a second insulating film, which is made of a substance with a lower diffusion coefficient for oxygen than the first insulating film, and which is disposed in the first insulating film or between the insulating film and the lower layer element. 1. A stacked structure semiconductor device comprising an insulating film.
シリコン窒化膜であることを特徴とする特許請求の範囲
第１項記載の積層構造半導体装置。(2) The second insulating film forming a part of the interlayer insulating film is
2. The stacked structure semiconductor device according to claim 1, wherein the layered structure semiconductor device is a silicon nitride film.
ームアニールにより単結晶化されたシリコン層上に形成
されたものであることを特徴とする特許請求の範囲第１
項記載の積層構造半導体装置。(3) The upper layer element is formed on a silicon layer deposited on the interlayer insulating film and made into a single crystal by beam annealing.
2. The stacked structure semiconductor device described in 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62005071A JPS63174348A (en) | 1987-01-14 | 1987-01-14 | Stacked structure semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62005071A JPS63174348A (en) | 1987-01-14 | 1987-01-14 | Stacked structure semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63174348A true JPS63174348A (en) | 1988-07-18 |
Family
ID=11601154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62005071A Pending JPS63174348A (en) | 1987-01-14 | 1987-01-14 | Stacked structure semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174348A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01132140A (en) * | 1987-08-19 | 1989-05-24 | Agency Of Ind Science & Technol | Formation of pattern |
| US5060050A (en) * | 1987-07-21 | 1991-10-22 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| JP2021509226A (en) * | 2017-12-27 | 2021-03-18 | マイクロン テクノロジー，インク． | An array of transistors and strings extending in the height direction of the memory cells |
| US11404571B2 (en) | 2017-07-10 | 2022-08-02 | Micron Technology, Inc. | Methods of forming NAND memory arrays |
| US11538919B2 (en) | 2021-02-23 | 2022-12-27 | Micron Technology, Inc. | Transistors and arrays of elevationally-extending strings of memory cells |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5890762A (en) * | 1981-11-25 | 1983-05-30 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-01-14 JP JP62005071A patent/JPS63174348A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5890762A (en) * | 1981-11-25 | 1983-05-30 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5060050A (en) * | 1987-07-21 | 1991-10-22 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| JPH01132140A (en) * | 1987-08-19 | 1989-05-24 | Agency Of Ind Science & Technol | Formation of pattern |
| US11404571B2 (en) | 2017-07-10 | 2022-08-02 | Micron Technology, Inc. | Methods of forming NAND memory arrays |
| JP2021509226A (en) * | 2017-12-27 | 2021-03-18 | マイクロン テクノロジー，インク． | An array of transistors and strings extending in the height direction of the memory cells |
| US11538919B2 (en) | 2021-02-23 | 2022-12-27 | Micron Technology, Inc. | Transistors and arrays of elevationally-extending strings of memory cells |
| US12170324B2 (en) | 2021-02-23 | 2024-12-17 | Lodestar Licensing Group Llc | Transistors and arrays of elevationally-extending strings of memory cells |
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