JPS63174143A - Exception event detection method in multiple computer systems - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] It has a plurality of central processing units (CPUs) and, for example, one service processor (SVP), and the service processor (SVP) is an exception to the central processing unit (CPU). In a computer system that processes events, the service processor (SVP) processes the central processing unit (CP) where the exception event occurred.
In order to solve the problem that it takes time to detect U),
The plurality of central processing units (CPs) are divided into a plurality of groups each having a certain number of units (for example, n units), and a "flag" is set for each group to record whether or not an exceptional event has occurred within the group. By providing the flag J (Status), the service processor (SVP) can
(Status) to detect the group in which the exceptional event has occurred, check the status of all central processing units (CPUs) that make up that group, and check the central processing unit (CPU) in which the exception event has occurred. It is designed to detect.

[Industrial application field]

The present invention provides a computer system having a plurality of central processing units (CPUs) and, for example, one service processor (SVP), in which the service processor (SVP) processes an exception event of the central processing unit (CPU). The present invention relates to a method for detecting a central processing unit (CPU) in which the exceptional event has occurred.

Recent artificial intelligence languages, such as Lisp (LISP).

As prolog (PI'1OLOG) and the like are put into practical use, the development of artificial intelligence systems using this language is progressing.

In this case, the artificial intelligence language, in particular PROLOG
In a source program written in the OG) language,
Generally, many processes can be executed in parallel, and depending on the content of the program's processing, the process may be divided into dozens or even several times.

In this way, by having a plurality of processors (central processing units (CPUs)) execute parts that can be executed in parallel in parallel, the overall processing capacity can be improved.

However, when a failure (exception event) occurs in any of the plurality of processors operating in parallel, there is a problem in that it takes a lot of time to detect the processor in which the failure has occurred. Effectively, an exception event detection scheme is needed to detect the failing processor.

[Prior art and problems to be solved by the invention] FIG. 2 is a diagram illustrating a conventional exceptional event detection method.

In this figure, Flag (If "mf") is a flag that records the occurrence of an exception event in each central processing unit (CPU) (1 to m). For example, at °1', the occurrence of the exception event is detected. In addition, Flag-
set is a signal indicating that an exceptional event has occurred in the central processing unit (CPLI) (1 to m).
ag) (If = mf).

In the conventional system, each central processing unit (C
Exception events that occur in CPU) (1 to m) are flags (Flag) in each central processing bag "t (CPU) (1 to m).
if-rtrf) and is in charge of maintenance and operation of the computer system composed of the plurality of central processing units (CPUs) (1 to m).
2, the flag (Flag) (if = m
By checking the state of f), the central processing unit (CPII) (1 to m) in which the exceptional event occurred was detected.

Therefore, the service processor (SVP) 2 uses the flags (Flag) (
if - mf) must be checked one by one, and in computer systems with a large number of central processing units (CPUs),
There is a problem in that it takes time to detect the central processing unit (CPU) in which the exceptional event has occurred.

In view of the above-mentioned conventional drawbacks, the present invention provides a computer system comprising a plurality of central processing units (CPUs).
It is an object of the present invention to provide an exceptional event detection method for quickly detecting an exceptional event (failure) occurring in any of the plurality of central processing units (CPUs).

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of an exceptional event detection method in a multiple computer system according to the present invention.

The present invention includes a plurality of central processing units (CPUs) (1 to m) and an external device 2, and the external device 2 is configured to control the plurality of central processing units (CPUs) (1 to m). In a computer system that processes exceptional events, the plurality of central processing units (CPUs) (1 to m) are divided into a plurality of groups (1a=k) for each specific unit number (n units).
a), and for each group (la ``ka),
A flag j (Status) (is-ks) is provided to record whether or not an exceptional event has occurred in the external device (2).
is ”ks), the group in which the exception event has occurred is
The central processing unit W (CPU) in which the exception event occurred is detected by detecting the group and checking the status of all central processing units (CPUs) (1 to n) that make up the group. Configure.

[Effect]

That is, according to the present invention, a plurality of central processing units (CPU
) and, for example, in a computer system that has one service processor (SVP) and the service processor (SVP) processes exception events of the central processing unit (CPU), the service processor (SVP) handles exception events of the central processing unit (CPU). In order to solve the problem that it takes time to detect the central processing unit (CPU) that has occurred,
U) is divided into multiple groups of a certain number of units (for example, n units), and for each group, a "Flag J (Status)" is used to record whether or not an exceptional event has occurred within the group.
By providing the above service processor (SV
P) detects the group in which the exception event has occurred based on the "flag" (Status), checks the status of all central processing units (CPUs) that make up the group, and detects the exception event. Since the central processing unit (CPU) in which the exceptional event has occurred is detected, the central processing unit (CPU) in which the exceptional event has occurred can be detected at high speed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing an example of the configuration of an exceptional event detection method in a multiple computer system according to the present invention, and shows a central processing unit (CPU) group divided into each group (la = ka).
Flag (Status) (1s
-ks) and a multiplexer (MPX) 3 that takes out the state of the flag (Flag) for each group are necessary means to implement the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

Hereinafter, with reference to FIG. 1, an explanation will be given of an exceptional event detection method in a computer system comprising a plurality of central processing units (CPUs) according to the present invention.

First, as an example, m central processing units (CPIJ) (
1 to m) is divided into groups of n units (la = ka) (k = m/n), and in the central processing unit (hereinafter referred to as CPU) 1 of group 1a, an exceptional event We will explain the case where this occurs.

(1) Operation of each circuit: In the initial state, the Flag-set of the CPU (1)
='o'+ Plug='o', and group (1
5tatus of a) = 'O'.

■ Here, if an exception event occurs in CPU (1) of group (1a), Flag-s of CPU (1)
et='l'.

(2) Flag-set='1' of CPU (1) sets F1ag='1' of CPU (1) + 5tatus(Is)='l' of group (1a).

(2) Operation in the service processor (SVP): In the initial state, the CPU (1) Flag-set='
o', Flag='O°, and group (1a
), 5tatus = 'Q', but Service Processor (SVP) 2 is for all groups (la Nka)
5 statuses (1s=ks) are confirmed in order.

(2) Here, an exception event occurs in CPU (1) of group (1a).

■ 5tatus (is) of group (1a) = 'l'
The detection unit 20 detects this, recognizes that an exceptional event has occurred in the group (Ia), and notifies the processing unit 21.

■ In the processing unit 21 of the service processor (SVP) 2, each central processing unit (CPU) (1 to n
) selection signal (
GS) and sends all Flags of the group (1a).
Check.

■ And Flag(if) of CPU (1) = '
1', the CPU (1) knows that an exceptional event has occurred.

As described above, the present invention provides a computer system having a plurality of CPUs and one service processor (SVP), in which the service processor (SVP) processes an exception event occurring in each CPU. CPUs are divided into groups by a certain number of units (for example, 10 units), and a flag (Status) is provided for each group to record whether or not an exception event has occurred within the group. When detects a group in which an exception event has occurred based on the flag (Status), the status G (Flag
), the CPU in which the exceptional event has occurred can be detected at high speed.

〔Effect of the invention〕

As explained in detail above, the exceptional event detection method for a multiple computer system of the present invention is applicable to multiple central processing units (C
For example, one service processor (SVP
), in which the service processor (SVP) processes an exception event of a central processing unit (CPU), the service processor (SVP) detects the central processing unit (CPU') in which the exception event has occurred. In order to solve the problem of time required, the plurality of central processing units (CPUs) are divided into groups of a certain number of units (for example, n units), and for each group, an exception event is detected within the group. [Flag J (Stat
By providing a flag J (Status), the service processor (SVP) can detect a group in which an exception event has occurred, and all central processing units (CPUs) constituting that group can ) Check the status of the central processing bag where the exception occurred? 1fE
(CPLI), the central processing unit (CPU) in which an exceptional event has occurred can be detected at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of an exceptional event detection method in a multiple computer system according to the present invention. FIG. 2 is a diagram illustrating a conventional exceptional event detection method. It is. In the drawings, 1 to II+ are central processing bags H (cpu). 1a-ka are groups. 1f to nf or IIIf are flags. l5-ks is a flag (Status). 2 is a service processor (SVP). 20 is a detection unit, and 21 is a processing unit. 3 is a multiplexer (MPX). are shown respectively. CPLICυ thing 2 圀

Claims (1)

[Claims] It has a plurality of central processing units (CPUs) (1 to m) and an external device (2), and the external device (2) is connected to the plurality of central processing units (CPUs) ( In a computer system that processes exception events (1 to m), the plurality of central processing units (CPUs) (1 to m) are divided into a plurality of groups (1a to ka) each having a specific number of units, and For each group (1a-ka), the group (1a-k
a) is provided with a "flag" (1s to ks) to record whether or not an exceptional event has occurred;
detects a group in which an exception has occurred, and all central processing units (CPUs) that make up that group are
) (1 to n) to detect a central processing unit (CPU) in which the exceptional event has occurred.