JPS63173123A - Digit aligning circuit - Google Patents

Abstract

PURPOSE:To perform digit alignment at high speed, by selecting an output exceeding zero out of the subtraction values of a first and a second data index parts or the second and the first data index parts, and performing digit alignment shift, in the digit alignment of a virtual part required for the addition/ subtraction of a floating point data in which a numeric numeric value is divided to an displayed as the virtual part and the index part. CONSTITUTION:At a first subtraction circuit 9, a subtraction processing in which the index part EB of a second floating point data FB is substracted from the index part EA of a first floating point data FA is performed, and at a second subtraction circuit, the index part EA is subtracted from the index part EB, and when a subtracted result is less than zero, a flag is attached. And the subtracted result exceeding zero is selected by a selector 11, and is supplied to a digit aligning shifter 7, and a digit aligned floating point data is processed at an addition/subtraction circuit 8. Therefore, a comparator for the index parts of both data FA and FB is not required, and a data path is shortened, then, the digit alignment can be performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mantissa digit adjustment circuit necessary for addition and subtraction of floating point data in which a numerical value is expressed separately into a mantissa and an exponent.

(Prior art) Figure 3 shows, for example, mantissa digit alignment used in a conventional floating-point ALU (arithmetic logic circuit) shown in Proceedings of the 1985 IEICE General Conference Proceedings 470 (P, 2-188). It is a block diagram of a circuit. In the figure, 1 is first floating point data F composed of exponent part data EA and mantissa part data MA.

signal line 2 is exponent data EB and mantissa data M
, 3 is an exponent comparison circuit for comparing the magnitudes of the exponent data EA and exponent data E, and 4 is an exponent comparison circuit for comparing the exponent data E and E8. a selector which distributes the numbers and inputs one as the minuend of the subtraction circuit 5 in the next stage and the other as the input of the subtrahend;
5 is a subtraction circuit for the input exponent data E, E;
6 is a selector that distributes the mantissa data M and M8 and outputs one of them to the next stage shifter 7 and the other to the addition/subtraction circuit 8; 7 is a shifter that aligns the mantissa data M and M8; 8 is an addition/subtraction circuit for the mantissa data MA, M whose digits have been aligned.

Next, the operation will be explained. Generally, when performing floating point addition and subtraction, the exponent parts of the two data to be operated on are aligned to the larger one, so the difference between the exponent parts is taken and the mantissa of the one with the smaller exponent part is calculated by this difference. It is necessary to shift the part data until the digit positions match. This process is generally called a digit alignment shift, and as a control signal for this shift, it was necessary to obtain the difference between the exponent parts as an absolute value (a value greater than or equal to zero). Therefore, the conventional digit matching circuit shown in FIG. 3 operates as follows.

That is, the exponent part comparison circuit 3 compares the exponent part data E and the exponent part data E8, and sends a control signal 3a representing the result to the selector 4 and the selector 6. In the selector 4, the larger data of the exponent part data EA and the exponent part data E8 is sent to the subtraction circuit 5 by the control signal 3a.
The input data of the minuend of is distributed such that the smaller data becomes the input data of the subtracted number of the subtraction circuit 5. Therefore, the subtraction result 5a of the subtraction circuit 5 is always greater than or equal to zero.

The subtraction result 5a becomes a control signal for the digit alignment shifter 7.

On the other hand, by the time the subtraction result 5a is output, the selector 6 uses the control signal 3a to change the data corresponding to the smaller of the exponent data E and E8 among the mantissa data MA and M to the input data of the shifter 7. Then, the other data is distributed so that it becomes the input data of the direct addition/subtraction circuit 8. Thereafter, the shifter 7 adjusts the digits of the mantissa data MA9MB by shifting the mantissa data M or M8 by the number of digits indicated by the 1IIIJ'wJ signal 5a, and outputs the resultant data to the addition/subtraction circuit 8. Then, in the addition/subtraction circuit 8, addition/subtraction is performed on the mantissa data MA, M whose digits have been aligned.

FIG. 4 is a flowchart showing the longest path in the conventional digit alignment process described above. As shown in FIG. 4, the longest path is the exponent part data E, E
Comparison of the magnitude of B (step Sl), selection of input data to the subtraction circuit 5 (steps S2 to S4), subtraction processing of exponent data E and E8 by the subtraction circuit 5 (step S5), and digit alignment by the shifter 7 Processing (step 86) occurs.

[Problem that the invention seeks to solve]

The conventional digit alignment circuit is configured as described above, and the subtraction of the exponent part data to obtain the digit alignment shift control signal is performed after the magnitude comparison of the exponent part data. The exponent part data must be subtracted until the process is completed. Therefore, there was a problem that processing time increased and speeding up could not be achieved.

This invention was made to solve the above-mentioned problems, and it is possible to subtract exponent data without comparing the exponent data, thereby eliminating the need for processing time for comparing the exponent data. The purpose is to obtain a digit alignment circuit that can speed up processing.

[Means for solving problems]

The digit alignment circuit according to the present invention receives first and second floating point data and subtracts exponent part data of the second floating point data from exponent part data of the first floating point data. a subtraction circuit; a second subtraction circuit that receives first and second floating point data and subtracts exponent part data of the first floating point data from exponent part data of the second floating point data; a selector that receives the outputs of the first and second subtraction circuits and selects zero or more outputs among them; and digit alignment of the mantissa data of the first and second floating point data according to the output results of the selector. The system is equipped with a shifter that performs the following steps.

[Effect]

In this invention, since two subtraction circuits are provided, one of the two subtraction results will always be a result greater than or equal to zero, and the result greater than or equal to zero is selected as the control signal to the shifter for digit alignment. Therefore, the longest path in the digit alignment process is subtraction of the exponent part data, selection of the subtraction result, and digit alignment.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a digit matching circuit according to the present invention. In the first factor, 1 is the signal line of the first floating point data FA composed of exponent data EA and mantissa data MA, and 2 is the signal line of the second floating point data composed of exponent data E8 and mantissa data M8. The signal line for decimal point data F, 9 is the first floating point data FA
10 is the exponent part data E of the second floating point data FB; , is input to the minuend, and the exponent part data EA of the first floating point data FA is input to the subtrahend. 11 is the output result 9a of the first subtraction circuit 9.
and a selector that selects one of the output results 10a of the second subtraction circuit 10 by the carry output 10b of the second subtraction circuit 10; 6 is the first floating point data FA;
The mantissa data MA of the second floating point data F and the mantissa data M of the second floating point data F are subtracted from the carrier output 10b of the subtraction circuit 10.
7 is a shifter that performs a digit alignment shift using the output 11a of the selector 11, and 8 is a digit-aligned mantissa data MA.
It is a 9 MB addition/subtraction circuit, and 1.2.6 to 8 are similar to the conventional circuit shown in FIG.

Next, the operation of the digit alignment circuit configured in this manner will be explained. The first subtraction circuit 9 calculates the value obtained by subtracting the exponent part data EB of the second floating point data FB from the exponent part data FA of the first floating point data FA, that is, (EA-
E3) is calculated.

On the other hand, in the second subtraction circuit 10, the value obtained by subtracting the exponent part data EA of the first floating point data FA from the exponent part data EB of the second floating point data FA, that is, (EB-
EA) is calculated. These subtraction results 98.10a are output to the selector 11, respectively.

The selector 11 selects a subtraction result 9a or 10 of zero or more by controlling the carry output 10b of the second subtraction circuit 10.
a is selected, and its output 11a becomes a control signal for the digit alignment shifter 7. That is, when (E - EA) is greater than or equal to zero, the carry output 1Ob becomes °"L II, and in response to this, the selector 11 selects the subtraction result 10a by the second subtraction circuit 10, that is, the value of (E - EA). .

Further, when (EB - E ) is negative, the carry output 10b becomes A "H11," and in response to this, the selector 11 outputs the subtraction result 9a from the first subtraction circuit 9, that is, (E, -E,)
Select a value.

At the same time as the selector 11 selects the subtraction results 9a and 10a, the selector 6 uses the carry output 10b of the second subtraction circuit 10 as a control signal to select the mantissa data of the first and second floating point data F and FB. Sorting of M and M is performed.

As a result of the distribution, the index part data FA and the index part data EB
The mantissa data 6a (one of the mantissa data M, M) corresponding to the smaller one of them is output to the shifter, and the other mantissa data 6b (the other of the mantissa data MA1MB)
is output to the addition/subtraction circuit 8. In other words, the selector 6 is
When the carry output 10b of the second subtraction circuit 10 is "L", (E - EA-) is greater than or equal to zero and the exponent data EA is the smaller data, so the corresponding mantissa data Output MA to shifter 7. Further, when the carry output 10b is "T+", (EB-E) is negative and the exponent part data E is the smaller data, so 1. The mantissa data M corresponding to this is output to the shifter 7.

The shifter 7 performs eight-digit alignment by shifting the mantissa data M or M by the number of digits indicated by the output 11a based on the output 11a from the selector 11, and after the digit alignment, the mantissa data 7a is output to the addition/subtraction circuit 8. Then, in the addition/subtraction circuit 8,
A floating point addition/subtraction operation is performed between the mantissa data 6b from the selector 6 and the mantissa data 7a after digit alignment.

As is clear from the above description, the longest path in the digit alignment process according to the present invention is the subtraction process of the exponent data by the first and second subtraction circuits (steps 87 and 38), as shown in the flowchart of FIG. ), selector 11
The selection of the subtraction result by (steps 89 to 511) and the digit alignment processing by the shifter 7 (step 512) are performed, and there is no need to compare the magnitude of the exponent part data as shown in FIG. 4, which shows the conventional example.

Further, in the above embodiment, the control signals to the selector 6 and the selector 11 are sent to the carry output 10b of the second subtraction circuit 10.
However, this control signal may be the carry output of the first subtraction circuit 9, or the output result 9a of the first subtraction circuit 9 or the output result 10a of the second subtraction circuit 10.
However, in these cases, the same effects as in the above embodiments can be achieved.

〔Effect of the invention〕

As explained above, according to the present invention, in the digit alignment circuit, an exponent data subtraction circuit, which is equivalent hardware G, is added in place of the exponent comparison circuit. Since we have eliminated the need for size comparison processing,
The longest path in the digit alignment process is subtraction of the exponent part data and selection of the subtraction result for 0 digit alignment, which has the effect of allowing the digit alignment process to be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the digit matching circuit according to the present invention, FIG. 2 is a flow chart of the longest path in the digit matching process according to the present invention, and FIG. 3 is a block diagram showing a conventional digit matching circuit. FIG. 4 is a flowchart of the longest path in conventional digit alignment processing. In the figure, 7 is a shifter, 9 is a first subtraction n circuit, 10 is a second subtraction circuit, and 11 is a selector. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) a first subtraction circuit that receives first and second floating point data and subtracts exponent data of the second floating point data from exponent data of the first floating point data; and a second subtraction circuit that receives second floating point data and subtracts exponent data of the first floating point data from exponent data of the second floating point data; A selector that receives the output of the subtraction circuit and selects an output of zero or more among them, and a shifter that aligns the digits of the mantissa data of the first and second floating point data according to the output result of the selector. Digit alignment circuit. (2) The selector selects the first and second subtraction circuits based on the carry output of either of the first and second subtraction circuits.
The digit matching circuit according to claim 1, which selects one of the outputs of the subtracting circuit.