JPS63172136U - - Google Patents
Info
- Publication number
- JPS63172136U JPS63172136U JP6565187U JP6565187U JPS63172136U JP S63172136 U JPS63172136 U JP S63172136U JP 6565187 U JP6565187 U JP 6565187U JP 6565187 U JP6565187 U JP 6565187U JP S63172136 U JPS63172136 U JP S63172136U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- small
- board
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第1図は、本考案による半導体パツケージの断
面図、第2図は第1図の半導体パツケージの底面
図である。
1……半導体パツケージの絶縁体、2……突起
、3……金属メツキ面。
FIG. 1 is a sectional view of a semiconductor package according to the present invention, and FIG. 2 is a bottom view of the semiconductor package of FIG. 1...Insulator of semiconductor package, 2...Protrusion, 3...Metal plating surface.
Claims (1)
この面に設けた少なくとも3つの小さな突起とを
有することを特徴とする小形半導体パツケージ。 The surface to be soldered onto the case or board, etc.,
A small semiconductor package characterized in that it has at least three small protrusions provided on this surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6565187U JPS63172136U (en) | 1987-04-28 | 1987-04-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6565187U JPS63172136U (en) | 1987-04-28 | 1987-04-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63172136U true JPS63172136U (en) | 1988-11-09 |
Family
ID=30902923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6565187U Pending JPS63172136U (en) | 1987-04-28 | 1987-04-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63172136U (en) |
-
1987
- 1987-04-28 JP JP6565187U patent/JPS63172136U/ja active Pending