JPS63171496A - Dual port memory controller - Google Patents

Abstract

PURPOSE:To shorten a transfer time without limiting a dual port memory in a constitution by decoding a data transfer timing signal and a data transfer cycle to the dual port memory. CONSTITUTION:A CRT controller 11 outputs display address data (a), (b) and a display synchronizing signal (c) according to the contents of a mode register therein. The signal (c) is inputted to an address timing circuit 13, the data transfer timing signal (f) generated by a display data residual quantity counter 14 and generate is decoded and a memory access timing signal (d) is generated. When it is inputted to the dual port memory 12, the data transfer cycle is carried out. In this case, the counter 14 takes the same value as the bit selecting counter of a data register in the memory 12, thereby, the timing in the data transfer can be detected. Accordingly, even during the display period of a CRT display device, the display data can be transferred to the display device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual port memory control device for displaying display data on a CRT display device using a dual port memory as a frame memory.

[Conventional technology]

A conventional dual-port memory control device transfers one horizontal scanning line worth of data to a data register inside the dual-port memory during the horizontal retrace period of the display for a CRT display device using dual-port memory. , the data was output during the display period.

[Problem that the invention seeks to solve]

Conventional dual-port memory control devices operate as described above, so a dual-port memory must be configured that can transfer and hold data for the horizontal display width at one time to an internal data register. There was a problem in that there was a limit to the memory configuration.

Further, since the amount of data for the horizontal display width and the amount of data transferred to the data register may not match, some portions of the dual port memory are not displayed. For example, as shown in FIG. 4, when transferring the contents of any row of four memory cells 1 to data register 2, which has the capacity of one row of memory cell 1, the amount of pixel data to be transferred (for example, 640 pixel) 3 is the capacity of the four data registers 2 (
For example, since the remaining amount is less than 1024 pixels (for example, 1024 pixels), there is a remaining amount of 4 (shaded area). For this reason, when performing DMA transfer from another input device into a memory cell, etc., it is necessary to match the capacity of the memory with the capacity of the data register, resulting in a remaining amount of memory, and the display data as shown in the memory map in Figure 5. Since the memory areas of the data are no longer continuous, the data must be transferred in units of horizontal display width, which poses a problem in that it takes a long time to transfer.

In FIG. 5, 5a, 6a, and 7a are display data for the first line, second line, and third line, and 5b is display data.

6b and 7b are the remaining amounts.

Furthermore, when attempting to migrate from a conventional single-port memory, there is a problem in that display memory maps become incompatible because the memory areas for display data are not contiguous.

The present invention has been made in view of these points, and its purpose is to make dual-port memory free from configuration limitations, short on transfer time, and compatible with single-port memory. There is a dual port memory controller to obtain.

[Means for solving problems]

A random access port that connects directly to multiple memory cells and the contents of any row of memory cells are transferred to a data register with the capacity of one row of memory cells, and data is serially input/output in synchronization with an external clock. In a dual-port memory control device for displaying display data on a raster display system display device using a dual-port memory with two ports, including a serial access port and a serial access port, the data transfer timing inside the dual-port memory is controlled. A display data remaining amount counter that is detected when a counter inside the dual port memory reaches a predetermined value, and a data transfer timing signal output from this display data remaining amount counter is decoded and data is transferred to the dual port memory. An access timing circuit for performing cycles is provided.

[Effect]

In the present invention, display data is transferred even during the display period.

〔Example〕

First, an overview of the dual port memory that constitutes the dual port memory control device will be explained.

Dual port memory is a memory for images that has a serial access port that can serially input and output data in addition to a normal random access port. A normal memory cell is connected to the random access port,
A data register with a capacity for one row of memory cells is connected to the serial access port. Any row in the memory cells can be transferred to the data register and output to the serial access port. The above two ports can operate asynchronously except for transfer control between the data register and memory cell. For this reason, compared to conventional single-port memory, when dual-port memory is used, the CPU can be accessed from the random access port even during the display period.
can be accessed, rendering efficiency is approximately doubled.

FIG. 2 is an operation timing chart of the dual port memory. The random access port is “RA 100” (Figure 2 (
a)), CAS (Fig. 2 (g))) and AO-A7 (
FIG. 2(C)). The serial access ports are located under yδ (Figure 2(d)) and SC (Figure 2(e)).
), and Sol~SO4(
The data is output in FIG. 2(r)). SC is used as a clock for a bit select counter of an internal data register. Also, DT/σ100 (Fig. 2 (gl
) is a signal for controlling transfer from an internal memory cell to a data register.

If this signal is at a low level at the rise of RAS, this memory cycle is regarded as a data transfer cycle.

An embodiment of a dual port memory control device according to the present invention is shown in FIG. In FIG. 1, reference numeral 11 indicates a display synchronization signal C9 and a C which generates display address data a and b.
RT controller, 12 is dual port memory, 13
14 is an access timing circuit that controls access to the dual port memory 12, 14 is a display data remaining amount counter, and 15 is a row address data a and a column (
column) multiplexer for switching address data b, 1
6 is a row address bus, and 17 is a column address bus. Further, d is a memory access timing signal, e is a row/column address switching signal, f is a data transfer timing signal, g is a data load signal to the display data remaining amount counter 14, and h is a control signal for the display data remaining amount counter 14. It is.

This device uses a display data remaining amount counter 14 as a control circuit for the dual port memory 12 to check the amount of display data remaining in the data register inside the dual port memory 12, so that timing for data transfer can be generated even during the display period. This is what I did.

The display data remaining amount counter 14 in this device has a bit width equivalent to five column address data of the dual port memory 12, and latches the column address data b internally when a data transfer cycle occurs. The count-up clock is the serial clock SC for the serial access port output of the dual port memory 12 (see Figure 2).
e)), and the serial enable signal SOE (FIG. 2(d)) of the dual port memory 12 is also used as the enable signal. Therefore, the display data remaining amount counter 14 has the same contents as the bit selection counter of the data register inside the dual port memory 12. Data transfer timing occurs when all bits of the counter rise.

In FIG. 1, the access timing signal d is RAS,
Consists of positive AS, digit/■100, SOE, and SC signals,
The control signal consists of SOE and SC signals. Q output of multiplexer 15 is address data AO
~A7.

Next, the operation of this device will be explained. CRT controller 11 outputs display address data a, b and display synchronization signal C according to the contents of an internal mode register. The display synchronization signal C is input to the address timing circuit 13, which decodes the data transfer timing signal f generated by the display data remaining amount counter 14 and generates the memory access timing signal d. When this is input to the dual port memory 12, a data transfer cycle is performed. The display address data a and b are divided into row address data a and column address data b and input to the multiplexer 15. In the multiplexer 15, the row address data a and the column address data b are Send column address data b to dual port memory 12.

The display data remaining amount counter 14 receives the serial enable signal “δ100” of the dual port memory 12.

A serial clock signal SC is used to control enable and clock. Further, the data load signal g becomes active during a data transfer cycle, and the load data at that time is column address data b used for data transfer. Therefore, the display data remaining amount counter 14 takes the same value as the bit selection counter of the data register inside the dual port memory 12, and the timing of data transfer can be determined.

In this way, in this device, the display data remaining amount counter 14 takes the same value as the bit select counter of the data register inside the dual port memory 12, so that the timing of data transfer can be detected. , display data can be transferred to the display device even during the display period of the CRT display device. As a result, there is no remaining capacity in the data register, and there is no need to match the memory cells in the dual port memory 12 to the data register, resulting in a memory map with no remaining capacity as shown in FIG. Time is also reduced. In FIG. 3, 5.6.7 is the display data of the 1st line, the 2nd line, and the 3rd line.

In the above embodiment, a display device is shown as a control target, but it can also be applied to other devices using dual port memory, and contrary to the above, when inputting to dual port memory from an image sensor etc. can also be applied.

〔Effect of the invention〕

As explained above, the present invention enables display data to be transferred even during the display period of the display device by detecting the data transfer timing, and it is not necessary to make the display data memory area discontinuous in order to match the data register. Since there are no configuration limitations, compatibility with single access port memory can be obtained, and even in the case of DMA transfer, there is an effect that the transfer can be performed at high speed.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing an embodiment of the dual port memory control device according to the present invention, Fig. 2 is a timing diagram showing internal signals of the dual port memory, and Fig. 3 is a system diagram showing an embodiment of the dual port memory control device according to the present invention. A data state diagram showing a memory map. FIG. 4 is an explanatory diagram showing the data state of a dual port memory in a conventional dual port memory control device. FIG. 5 is a memory map of a dual port memory under control by a conventional dual port memory control device. It is a data state diagram shown. 11... CRT controller, 12... Dual port memory, 13... Access timing circuit, 14
. . . Display data remaining amount counter, 15 . . . Multiplexer, 16 . . . Row address bus, 17 . . . Column address bus.

Claims (2)

[Claims] (1) A random access port that directly connects to multiple memory cells, and the contents of any row of the memory cells are transferred to a data register with the capacity of one row of the memory cells, synchronized with an external clock, and serialized. In a dual port memory control device for displaying display data on a raster display system display device using a dual port memory having two ports, a serial access port and a serial access port for inputting and outputting data, as a frame memory, the dual port memory A display data remaining amount counter detects the internal data transfer timing when a counter inside the dual port memory reaches a predetermined value, and a data transfer timing signal output from this display data remaining amount counter is decoded and the dual port A dual-port memory control device comprising: an access timing circuit that causes a memory to perform a data transfer cycle. (2) The display data remaining amount counter has the same number of bits as the column address data width of the dual port memory, and when a transfer cycle occurs, it latches the column address data on the column address bus and transfers this column address data to the next column address data. The dual port memory control device according to claim 1, wherein the dual port memory control device is used for detecting timing of data transfer.