JPS63168578A - Test of binary counter - Google Patents

Abstract

PURPOSE:To achieve a reduction in testing time of a counter counting function, by setting a specified digit bit to 1 or 0 as counting initial value at the test of function to compare the results of counting by the inputting of counts in one counting with an expected value. CONSTITUTION:At the test of increment counting function, bit below any digit existing at a PROM 2 is set to 1, and that above the existing digit to 0 as counting initial value. As counting expected value, bit corresponding to any digit existing at a PROM 3 is set to 1 while that of the digit other than that therein to 0. Then, numerals of the ROM 2 are inputted into counters C0-C3. Therefore, one clock is inputted into an input terminal CLK for increment counting, an output thereof is inputted into a comparator circuit 4 from output terminals Q00-Q1F and compared with a value inputted from the ROM 3 to make sure that the increment counting function is normal. At the test of a decrement counting function, it is so set that the previous value of the ROM 3 is outputted to the ROM 2 while the previous value of the ROM 2 to the ROM 3 as counting initial value, and then, the operation is performed as mentioned above.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a test method for checking the counting function of a multi-bit binary counter.

(Prior Art) Generally, a test to confirm the counting function of a counter is performed by the method shown below.

First, all counts of the counter are cleared and all bits of the counts are set to "0".

After this, for example, when this counter is binary n bits, 21 counting clocks are input.

Then, confirm that the count result is "n" in decimal code.

(Problems to be solved by the invention) In recent years, arithmetic circuits such as microcomputers have
There is a trend toward multi-bit processing for the purpose of faster processing. That is, the number of bits increases from 8 bits to 16 bits and then to 32 bits, and the above-mentioned counter is also made to have multiple bits.

In this case, a conventional test for checking the counting function of a counter has a problem in that the test time becomes enormous as the number of bits increases. For example, if this counter is a 32-bit binary counter and the period of the counting clock is IB, a time of 10X2" = 4X10" s is required just for the up-counting function test.

The present invention was made in response to this situation.
It is an object of the present invention to provide a binary counter testing method that can shorten the test time for checking the counting function of a multi-bit counter.

[Structure of the invention] (Means for solving the problem) That is, the method of the present invention includes an up-count function and/or
In a test method for checking the counting function of a multi-bit binary counter that has a down-count function and can be set to an initial count value, when testing the up-count function,
As the initial counting value, set the bits below a predetermined digit to "1" and the bits exceeding the digit to "0", then input one counting clock and set the expected value of the counting result set in advance. When comparing the down count function test ↓,
As the initial counting value, set the bits of a predetermined digit to "1" and the bits of other digits to 'O', then input one counting clock and expect the preset counting result. It is characterized by comparing with the value.

(Function) The present invention uses the method described above to carry a predetermined bit.
To confirm the trg or carry down function, it is only necessary to input one counting clock. This makes it possible to shorten the test time for checking the counting function of the multi-bit counter.

(Embodiment) Hereinafter, an embodiment in which the method of the present invention is applied to a counting function confirmation test of a 32-bit binary counter formed by connecting 8-bit binary counters in series will be described in detail with reference to the drawings.

Figure 1 is a circuit diagram showing the configuration of the 32-bit binary counter. In the figure, Co"C3 indicates an 8-bit binary counter, and Doo~'D and F indicate the initial count value of 32 bits. The input terminals Qoo to Q+F are output terminals to which 32-bit counting results are output.Furthermore, LOAD outputs the count initial values set in the input terminals I)oo to D and F to each counter Co to C1. CLK is an input terminal to which a counting clock is input, and UP/DOWN is a control terminal 9p to which a control signal for switching between up-counting and down-counting is inputted.

Next, FIG. 2 shows a block diagram of a device for testing the counting function of this counter.

In the same figure, reference numeral 1 is the 32-bit binary counter shown in FIG.
A ROM (programmable ROM) 2 is connected. In addition, code 3 is the FRO in which the expected value of the counting result is stored.
The output of the FROM 3 is input to the comparator circuit 4 together with the output of the output terminal Qoo=Q+F of the 32-bit binary counter 1, and the results of these comparisons are output from the comparator circuit 4.

FIG. 3 is a diagram showing the contents stored in the above-mentioned FROM 2.3. Note that each number sequence in this figure is 3
This is a 2-bit numerical value expressed using hexadecimal notation.

In addition, in the figure, the numbers on the A side are all combinations of bits below a certain digit being 1" and bits exceeding that digit being "0", and the numbers on the B side are all combinations of bits below a certain digit being "1".
'', the bits of digits other than the corresponding digit are "0".

Then, during the up-count avg test, settings are made so that the value on the A side is output to FROM2 as the initial count value, and the value on the B side is output to FROM3 as the expected value of the count result.

Next, set the first column of numbers on the A side in FROM2 to the input terminals Doo to DIF of the 32-bit binary counter 1,
By inputting a control signal to the control terminal LOAD, it is input to the counter Co''C3.

After that, one counting clock is input to the input terminal CLK to count up. As a result, this 32-bit 2
When the up-counting function of the decimal counter 1 is normal, the bit having "1" is carried over and becomes the same as the corresponding B-side value (first column).

In other words, this counted up output is sent to the output terminal Q.
By inputting from oa to Q+F to the comparator circuit 4 and comparing it with the first column of the B side numerical value input from FROM 3, 1'° of the 32-bit binary counter 1 is calculated from these comparison results.
It is confirmed whether the up-counting function of the bit having .

Hereinafter, by performing such a comparison test up to the 32nd column, it is confirmed whether or not the up-counting function of all bits is normal.

In this way, in the up-count function test of this example,
For example, when the period of the counting clock is 1 tiger, the test time is 1g×32=32Ils, which significantly reduces the test time compared to the conventional method.

In addition, when testing the down count function, by setting the value on the B side to FROM 2 as the initial counting value and the value on the A side to FROM 3 as the expected value of the counting result, the result will be the same as in the above example. The explanation will be omitted because it can be done in the following manner.

[Effects of the Invention] As explained above, according to the binary counter testing method of the present invention, the test time for checking the counting function of a multi-bit counter can be significantly shortened compared to the conventional method. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a 32-bit binary counter according to an embodiment of the present invention, FIG. 2 is a block diagram of a device for testing the counting function of the counter according to this embodiment, and FIG. The figure shows the contents stored in the F ROM 2.3 in this embodiment. 1...32-bit binary counter 2.3...FROM 4...Comparison circuit Co "C3...8-bit binary Counter Doo'-D+F ...Input terminal Qoo~Q+r ...Output terminal Applicant Toshiba Corporation Agent Patent attorney Sasu Suyama - Figure 1

Claims (2)

[Claims] (1) In a test method for checking the counting function of a multi-bit binary counter that has an up-counting function and/or a down-counting function and can be set to an initial counting value, (a) when testing the up-counting function, As an initial value, set the bits below a predetermined digit to "1" and the bits exceeding the digit to "0", then input one counting clock and compare it with the expected value of the counting result set in advance. (b) When testing the down count function, set the bits of a specified digit to "1" as the initial count value, set the bits of other digits to "0", and then run one counting clock. A method for testing a binary counter, which comprises inputting data and comparing it with a preset expected value of a counting result. (2) The method for testing a binary counter according to claim 1, wherein the initial count value and the expected value of the count result are stored in a semiconductor memory.