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JPS63168044A - Semiconductor chip mounting structure - Google Patents

Semiconductor chip mounting structure

Info

Publication number
JPS63168044A
JPS63168044A JP61310945A JP31094586A JPS63168044A JP S63168044 A JPS63168044 A JP S63168044A JP 61310945 A JP61310945 A JP 61310945A JP 31094586 A JP31094586 A JP 31094586A JP S63168044 A JPS63168044 A JP S63168044A
Authority
JP
Japan
Prior art keywords
chips
laminated material
chamber
semiconductor chip
chambers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61310945A
Other languages
Japanese (ja)
Inventor
Naoaki Inoue
井上 尚明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP61310945A priority Critical patent/JPS63168044A/en
Publication of JPS63168044A publication Critical patent/JPS63168044A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To contrive a high density packaging of IC chips and so on by a method wherein the semiconductor chips are housed in the interiors of chambers to extend in the direction to intersect orthogonally the laminated direction of a laminated material and each electrode lead-out terminal of the chips is connected to each terminal formed on the surface of the laminated material through wiring groups. CONSTITUTION:Chambers 2 to extend in the direction to intersect orthogonally the laminated direction of a laminated material 1 are provided in the laminated material 1 formed by laminating plural sheets of substrates 1a, 1b.... Semiconductor chips 3 are housed in the interiors of the chambers 2 and each electrode lead-out terminal of the semiconductor chips 3 is connected to each terminal 6a, 6b... formed on the surface of the laminated material 1 through contact groups 4a, 4b... formed in the chambers 2 and wiring groups 5 provided on the surface of each substrate 1a, 1b.... Thereby, the chips 3 can be subjected to three-dimensional packaging and also, the wirings between the chips also become possible three-dimensionally in the laminated material 1 and a circuit can be brought into the state of higher density.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、rc等の半導体チップの3次元実装構造に関
する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a three-dimensional mounting structure of a semiconductor chip such as an RC.

〈従来の技術〉 ICチップ等の実装方法としては、従来、チップをパッ
ケージ内に収容して回路基板上に組み込む方法が一般的
で、他にチップオンボードあるいはフリップチップ法等
のチップを直接回路基板上に固着する方法もある。
<Prior art> Conventionally, the conventional method for mounting IC chips, etc. has been to house the chip in a package and mount it on a circuit board.Other methods include chip-on-board and flip-chip methods, in which the chip is directly mounted on a circuit. There is also a method of fixing it on a substrate.

〈発明が解決しようとする問題点〉 従来の実装方法によれば、いずれも、平面状の基板上に
デツプを載せるから、チップ間の接続は平面的なものと
なり、実装の高密度化には限界がある。
<Problems to be solved by the invention> According to conventional mounting methods, the chips are mounted on a flat substrate, so the connections between chips are flat, making it difficult to achieve high density packaging. There is a limit.

このことは例えば、センサ素子を2次元方向に配列して
なる旧型センサと、その各センサ素子の出力信号を入力
する処理回路との組み合わせにおいて、処理回路は旧型
センサに比して相当大型となってしまい、その結果、こ
れらを別個に設けてケーブルにより互いに接続する構造
となる。ここで、センサとその信号処理回路との距離は
、センサ出力が微弱な場合、あるいは連続的に高速度の
処理・対応が必要な場合、極めて重要な要素となる。す
なわち、この距離が長ければ長い程、多くのノイズをひ
ろったり、信号自体の減衰も大きくなってしまい、セン
サ自体の性能をはるかに上まわる障害となる場合がある
This means, for example, that when combining an old sensor with sensor elements arranged in a two-dimensional direction and a processing circuit that inputs the output signals of each sensor element, the processing circuit becomes considerably larger than the old sensor. As a result, a structure is created in which these are provided separately and connected to each other by cables. Here, the distance between the sensor and its signal processing circuit becomes an extremely important factor when the sensor output is weak or when continuous high-speed processing and response is required. That is, the longer this distance is, the more noise is picked up and the signal itself is attenuated more, which may cause problems that far exceed the performance of the sensor itself.

本発明は上記のような事情に鑑みてなされたもので、I
Cチ・ノブ等を高密度に実装し得る構造の提供を目的と
している。
The present invention was made in view of the above circumstances, and I
The purpose is to provide a structure that allows high-density mounting of C-chi, knobs, etc.

く問題点を解決するための手段〉 上記目的を達成するための構成を、実施例に対応する第
1図および第2図を参照しつつ説明すると、本発明は、
複数枚の基板1a、lb−を積層してなる積層体1に、
その積層方向寸法交する方向に伸びる室2を設けてその
内部に半導体チップ3を収容するとともに、その半導体
3の各電極取り出し端子を、室2内に形成された接点群
4a。
Means for Solving the Problems> The configuration for achieving the above object will be described with reference to FIGS. 1 and 2 corresponding to the embodiment.
A laminate 1 formed by laminating a plurality of substrates 1a and lb-,
A chamber 2 extending in a direction intersecting the stacking direction is provided, and a semiconductor chip 3 is housed inside the chamber 2, and each electrode terminal of the semiconductor 3 is connected to a contact group 4a formed in the chamber 2.

4b・・・および各基板1a、lb−・−表面に設けら
れた配線群5を介して、積層体1の表面に形成された各
端子5a、5b・・−とそれぞれ接続したことによって
、特徴づけられる。
4b... and the respective terminals 5a, 5b... formed on the surface of the laminate 1 through the wiring group 5 provided on the surface of each substrate 1a, lb-... can be attached.

く作用〉 半導体チップ2を3次元実装でき、かつ、各チップ間の
配線も積層体1内において3次元的に可能となって、回
路の高密度化が達成できる。
Effects> The semiconductor chips 2 can be three-dimensionally mounted, and the wiring between the chips can also be three-dimensionally carried out within the stacked body 1, so that high density circuits can be achieved.

〈実施例〉 本発明の実施例を、以下、図面に基づいて説明する。<Example> Embodiments of the present invention will be described below based on the drawings.

第1図は本発明実施例の外観斜視図で、第2図はその要
部分解斜視図である。
FIG. 1 is an external perspective view of an embodiment of the present invention, and FIG. 2 is an exploded perspective view of the main parts thereof.

複数枚の基板ia、lb、・−21nを互いに積層して
形成された積層体1には、基板積層方向と直交する方向
に伸びる室2が設けられており、この室2の内部にペア
チップlC3が収容されている。
A stacked body 1 formed by stacking a plurality of substrates ia, lb, -21n on each other is provided with a chamber 2 extending in a direction perpendicular to the substrate stacking direction. is accommodated.

室2の底面には、第2図に示すように、その内部に収容
するベアチップIC3の電極取り出し端子の配設パター
ンに対応してバンプ接点4a、4b−が形成されており
、このバンブ接点4a、4b−はそれぞれ対向するペア
チップIC3の各電極取り出し端子と相互に接続され、
また、これによってペアチップIC3は室2内に固着さ
れる。
As shown in FIG. 2, bump contacts 4a and 4b are formed on the bottom of the chamber 2 in correspondence with the arrangement pattern of the electrode lead-out terminals of the bare chip IC 3 accommodated therein. , 4b- are mutually connected to each electrode extraction terminal of the pair chip IC3 facing each other,
Moreover, the paired chip IC3 is fixed in the chamber 2 by this.

室2内の各バンブ接点4a、4b・−は、各基板la、
1b−・−の表面に形成された配線群5によって、基j
Fi l a、  1 b−の側面に形成された各接点
6a、6b−・・と接続されている。これにより、積層
体1の室z内に収容されたペアチップIC3の各電極取
り出し端子は、3次元的に積層体1の表面にまで導出さ
れる。また、積層体1内の各チップ間の接続も、同様に
各基板ia、lb・・−表面の配線群5によって行われ
る。
Each bump contact 4a, 4b, - in the chamber 2 is connected to each board la,
By the wiring group 5 formed on the surface of 1b-.-, the group j
It is connected to each contact point 6a, 6b-... formed on the side surface of Fila, 1b-. Thereby, each electrode extraction terminal of the paired chip IC3 accommodated in the chamber z of the stacked body 1 is three-dimensionally led out to the surface of the stacked body 1. Further, the connections between the chips in the stacked body 1 are similarly made by the wiring group 5 on the surface of each substrate ia, lb, . . . .

室2の断面の大きさは、内部に収容するペアチップIC
3の断面よりもやや太き(設定されており、ICの使用
時においてファン等による冷却用の通風孔として利用さ
れ、熱対策が講じられている。
The size of the cross section of chamber 2 is determined by the size of the paired chip IC accommodated inside.
It is set to be slightly thicker than the cross section of No. 3, and is used as a ventilation hole for cooling by a fan or the like when the IC is in use, and is used as a heat countermeasure.

以上の本発明実施例において、各基板la、lb・−の
厚さはペアチップIC3の電極取り出し端子間寸法に応
じて、フィルム状等の薄いものを含めて任意に選定され
、全体としての積層体1の積層方向寸法は最低ベアチッ
プIC3の長さ寸法と同等でよい。その結果、例えば第
1図に示すように、センサS−Sを2次元方向に配列し
てなる固型センサAの面積とほぼ同等の端面面積のもと
に、各センサSの出力を独立に処理し得る信号処理回路
ユニットを組むことができる。このとき、各センサSの
有感面と反対側の面をそれぞれビングリッドアレイ (
図示せず)等によって接点6a、6b・−と接続する。
In the above-described embodiments of the present invention, the thickness of each substrate la, lb. The dimension in the stacking direction of 1 may be at least equal to the length dimension of the bare chip IC3. As a result, as shown in FIG. 1, for example, the output of each sensor S can be independently controlled based on the end surface area that is almost the same as the area of the solid sensor A, which is formed by arranging sensors S-S in a two-dimensional direction. A signal processing circuit unit capable of processing can be assembled. At this time, the surface opposite to the sensitive surface of each sensor S is arranged in a bin grid array (
(not shown) etc. to connect to the contacts 6a, 6b, -.

これにより、固型センサAのプローブ自体に信号処理機
能を持たせることもできる。
Thereby, the probe itself of the solid sensor A can be provided with a signal processing function.

なお、以上の実施例において、各基板1a、lb・−を
それぞれエポキシ系の硬い基板で構成したとき、その表
面の配線群5と室2内のバンブ接点4a。
In addition, in the above embodiment, when each board 1a, lb.

4b・−との接続が、エツジ部分において困難となる場
合もあるが、この場合、第3図に示すように、各エポキ
シ系基板31の表面にフィルム状のフレキシブルプリン
ト配線基板32等を貼着し、そのフレキシブル配線基板
32に配線群5およびバンプ接点4a、4b−を形成し
て、バンプ接点4a。
4b and - may be difficult at the edge portion, in this case, as shown in FIG. Then, the wiring group 5 and the bump contacts 4a, 4b- are formed on the flexible wiring board 32 to form the bump contact 4a.

4b−・−・の形成部分のみ室2の内方に折り曲げてそ
の底面に貼着することにより、対処することができる。
This can be solved by bending only the portions 4b--... inward of the chamber 2 and attaching them to the bottom surface of the chamber 2.

また、以上の実施例では、ペアチップIC3を室2内に
収容した例を示したが、回路密度をさほど高密度化する
必要のない場合には、パッケージされたIC等を室2内
に収容してもよい。
Further, in the above embodiment, an example was shown in which the paired chip IC 3 was housed in the chamber 2, but if there is no need to increase the circuit density so much, a packaged IC etc. may be housed in the chamber 2. It's okay.

〈発明の効果〉 以上説明したように、本発明によれば、基板を複数枚積
層してなる積層体に、積層方向に伸びる室を形成してそ
の内部に半導体チップを収容し、この半導体チップの各
電極取り出し端子を、室内の接点および各基板の表面に
設けられた配線群を介して、積層体表面の接点に接続し
たから、半導体チップを3次元的に高密度に実装するこ
とができ、例えばセンサの信号処理回路に適用してその
回路の高密度化をはかることにより、センサ大の信号処
理回路を得て、センサと密着状態で接続することが可能
となる。このことは、前述したようにプローブ内に信号
処理回路を組み込むことも可能となり、センサと信号処
理回路間の距離を著しく短縮化し得ることになり、セン
サ性能を害うことなくS/Nのよい検出が可能となる。
<Effects of the Invention> As explained above, according to the present invention, a chamber extending in the stacking direction is formed in a stacked body formed by stacking a plurality of substrates, a semiconductor chip is housed inside the chamber, and the semiconductor chip is Since each electrode lead-out terminal is connected to the contact point on the surface of the laminate through the contact point in the room and the wiring group provided on the surface of each board, semiconductor chips can be mounted three-dimensionally and with high density. For example, by applying the present invention to a signal processing circuit of a sensor to increase the density of the circuit, it becomes possible to obtain a signal processing circuit as large as the sensor and to connect it closely to the sensor. This makes it possible to incorporate a signal processing circuit into the probe as described above, and the distance between the sensor and the signal processing circuit can be significantly shortened, resulting in a good signal-to-noise ratio without impairing sensor performance. Detection becomes possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の外観斜視図、 第2図はその要部分解斜視図、 第3図は本発明の他の実施例の要部斜視図である。 1・・・積層体 la、lb、−−1n・・・基板 2・・・室 3・・・ベアチップIC 4a、4b・・・バンプ接点 5・・・配線群 6a、6b・・・端子 FIG. 1 is an external perspective view of an embodiment of the present invention; Figure 2 is an exploded perspective view of the main parts. FIG. 3 is a perspective view of essential parts of another embodiment of the present invention. 1... Laminated body la, lb, --1n...substrate 2...room 3...Bare chip IC 4a, 4b...bump contacts 5...Wiring group 6a, 6b...terminals

Claims (1)

【特許請求の範囲】[Claims] 複数枚の基板を積層してなる積層体に、その積層方向と
直交する方向に伸びる室を設けてその内部に半導体チッ
プを収容するとともに、その半導体チップの各電極取り
出し端子を、上記室内に形成された接点群および上記各
基板表面に設けられた配線群を介して、上記積層体表面
に形成された各端子とそれぞれ接続してなる、半導体チ
ップの実装構造。
A laminate formed by laminating a plurality of substrates is provided with a chamber extending in a direction perpendicular to the lamination direction, a semiconductor chip is housed inside the chamber, and each electrode lead-out terminal of the semiconductor chip is formed in the chamber. A semiconductor chip mounting structure in which the semiconductor chip is connected to each terminal formed on the surface of the laminate through a group of contacts and a group of wirings provided on the surface of each of the substrates.
JP61310945A 1986-12-29 1986-12-29 Semiconductor chip mounting structure Pending JPS63168044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61310945A JPS63168044A (en) 1986-12-29 1986-12-29 Semiconductor chip mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61310945A JPS63168044A (en) 1986-12-29 1986-12-29 Semiconductor chip mounting structure

Publications (1)

Publication Number Publication Date
JPS63168044A true JPS63168044A (en) 1988-07-12

Family

ID=18011278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61310945A Pending JPS63168044A (en) 1986-12-29 1986-12-29 Semiconductor chip mounting structure

Country Status (1)

Country Link
JP (1) JPS63168044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231304A (en) * 1989-07-27 1993-07-27 Grumman Aerospace Corporation Framed chip hybrid stacked layer assembly

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231304A (en) * 1989-07-27 1993-07-27 Grumman Aerospace Corporation Framed chip hybrid stacked layer assembly

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