JPS63164526A - Level converter - Google Patents

Abstract

PURPOSE:To attain drive based upon TTL level input by using a COMS inverter for an initial stage inverter and selecting the gn ratio of a P-channel transistor(TR) to an N-channel TR to reduce a circuit threshold. CONSTITUTION:The titled level converter has the initial stage inverter 11 and a CMOS level shifting circuit 14 connected to the post stage of the initial stage inverter 11. the initial stage inverter 11 has a serial circuit consisting of a load resistor RL connected between the 1st power supply node having the 1st power supply voltage VCC and an earth terminal and a CMOS inverter. The CMOS inverter consists of the P channel TR Q11 and the N channel TR Q12. A CMOS level shifting circuit 14 uses the 2nd power supply voltage VDD as an operation power supply.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a level converter formed within a semiconductor integrated circuit, and particularly relates to a level converter formed in a semiconductor integrated circuit, and particularly to a level converter formed in a semiconductor integrated circuit, and in particular, a level converter formed in a semiconductor integrated circuit. It is used as an interface between electrically insulated dart type) circuits.

(Prior Art) A conventional level converter was constructed as shown in FIG. In other words, a resistive load type MO using a low voltage power supply
It has an S inverter 91 at the first stage, and a high voltage power supply vD at the next stage.
It has a CMOS level shift circuit 92 using VT), followed by a CMOS inverter 93 using VT)D power supply.
94. The first stage inverter 9 above is
Since it is composed of an N-channel transistor Q91 and a resistor R, when a high level "H" potential is applied to the input and the transistor Q91 turns on, vcc
A through current Icc expressed by the following equation flows between the power supply and the ground terminal.

Here, S RON is the on-resistance of the first stage transistor Q91. This current ICc has a very large value for the 0M08 circuit, and can be considered as a static consumption current, so a large value is a fatal problem for the Fi 0M08 circuit.

However, if you try to drive the above level converter with TTL level input, the first stage transistor Q? In order to increase the transconductance of 17 m, the channel width must be made very large or the value of the load resistance R must be increased. However, in the former case, there is a problem that the through current Ice increases when the first stage transistor Q91 is turned on, and in the latter case, the transfer time tpd
There is a problem in that the amount increases.

Furthermore, in the above level comparator, the diode D//'i formed between the vcc power supply node and the DD power supply node has its anode side connected to the vcct source node and its cathode side connected to the vDD power supply node.
If c≦vDD, it can only be used as an interface from a low-voltage power supply system to a high-voltage power supply circuit (for example, an interface from a TTL circuit to a 0M08 circuit).

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problem that driving with a TTL level input results in an increase in through current and an increase in transmission time. in,
Even when driving with TTL level input, it is possible to convert to CMOS level without increasing the through current or increasing the transmission time, and it is possible to convert any voltage between the low voltage power supply circuit and the high voltage power supply circuit. It is an object of the present invention to provide a level converter that can easily be provided with a bidirectional interface function capable of converting levels in one direction.

[Structure of the Invention] (Means for Solving the Problems) The level converter of the present invention includes a load connected in series between a first power supply node having a first power supply voltage and a ground terminal. A first-stage inverter having a resistor and a CMOS inverter, and a CMOS level shift circuit using a second power supply voltage as an operating power supply at a stage subsequent to the first-stage inverter, and these are formed on the same semiconductor chip. .

(Function) In the first-stage inverter, the CMOS inverter to which the first power supply voltage is supplied via the load resistor has - the gm of its P-channel transistor and N-channel transistor;
By selecting the ratio, the circuit threshold value can be lowered sufficiently, so that driving by TTL level input becomes possible. Furthermore, since the first stage inverter uses a CMOS inverter, it is possible to suppress the through current.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. The level converter shown in FIG. 1 is a semiconductor integrated circuit, and 11 is a first-stage inverter, and a load resistor RL and a CMOS inverter ( (consisting of a P-channel transistor Q11 and an N-channel transistor Q12) are connected in series. Eleventh and second CMOS inverters 12 and 13, each using the power supply voltage vcc as an operating power supply, are connected in cascade to the output node of this CMOS inverter. The respective outputs of the two-stage inverters 12 and 13 are input to a CMOS level shift circuit 14 which uses the second power supply voltage vDD as an operating power supply, and the vDD power supply is operated on the output side of this level shift circuit 14. The third power source. A fourth CMOS inverter 6-15.16 is cascaded. In addition, each CMO above
As shown in FIG. 2, the S inverters 12.13 and 15.16 are connected to a P channel transistor Q21 and an N channel transistor Q2□.

In the above level converter, first stage in/? -ta 1
1, VCC power is supplied to the CMOS inverter via a load resistor tag, so the P-channel transistor Q11 and N-channel transistor Q1 of the CMOS inverter
By selecting a gm ratio of 2, the circuit threshold value can be sufficiently lowered, and therefore driving by TTL level input becomes possible. Also, the first stage inverter 1 is CM
Since an OS inverter is used, it is possible to suppress the through current compared to the case of using a conventional inverter consisting of an N-channel transistor and a load resistor. time t p d
It almost never leads to an increase in

FIG. 3 shows a level converter according to another embodiment. Compared to the level converter shown in FIG.
The power supply node is connected to an N-channel transistor Q3. The input gate 11 of the first stage as described above, the first CMOS
The difference is that it is connected to each power supply node of the inverter 12 and the second CMOS inverter 13, the dart of this transistor Q51 is connected to the vDD power supply node, and its substrate bias is set to the same potential as the source. Since they are the same, the same reference numerals as in FIG. 1 are given.

In the above level converter, since the resistor rate of the P-channel transistor is connected to the vDD potential, when Vcc<vDD, the threshold voltage (vTHP) decreases due to the pack r-) bias effect.

Therefore, even if the high level of the input voltage of the first stage inverter 11 is as low as A of the vcc power supply voltage, V□
Since p<Vasp is maintained, the P-channel transistor 1. is in the off state 6. ! 7. Since gm is large, N-channel transistor Q12 is turned on. Also, the source voltage of P-channel transistor Q11 is equal to load resistance RL.
The VCC power supply voltage will be lower due to the voltage drop.
rHP and V first. S is also small, and V when the input voltage of the first stage inverter 11 is low level. IIP<
The relationship of vTHP is maintained and the P-channel transistor RO 1
．． turns on. That is, even if the input voltage (especially high level) is lower than the vcc power supply voltage, it is possible to drive the first stage inverter 11 with small current consumption.

Further, the drain of the N-channel transistor Q31 is connected to the ■cc potential, the r-t to the VDD potential, and the source to the substrate (P well of the N-type semiconductor substrate).
Since current is prevented from flowing between the vcc power supply and the vDD power supply, it can be used in either case of vcc≦VDD or vDD<vcc. That is, not only level conversion from a circuit of a low voltage power supply system to a circuit of a high voltage power supply system, but also level conversion in the opposite direction is possible.

FIG. 4 shows a level converter according to yet another embodiment. 4 and 42 are a first clocked inverter and a second clocked inverter at the first stage, respectively, one of which is selected to be in an operable state by complementary selection signals M and M; The first clocked inverter 4 has a low circuit threshold so that it can be driven with a TTL level input, and the second clocked inverter 42 has a circuit threshold that can be driven with a FiCMOS level input. That is, the first clocked inverter 4 has P channel transistors Q41 and N
A CMOS inverter consisting of a channel transistor Q42 is connected between a low voltage power supply vcc node and a ground terminal, and a load resistor (MO8 resistor, diffused resistor 1.j) is connected between the vcc node and the source of the P channel transistor Q41.
? RL (can be realized with IJ silicon resistor, etc.) is inserted, and complementary selection signals M and M are respectively input to the dart between this P channel transistor Q41 and the N channel transistor Q42. Transistor Q43 and N-channel transistor Q44 are inserted in series, and these switching transistors Q and Q
The drain interconnection point of the output node is the output node. Further, the second clocked inverter 42 includes a P channel transistor Q45 and an N channel transistor Q45.
A CMOS inverter consisting of 46 is connected between the vcc node and the ground terminal, and complementary selection signals M and M are respectively input to the dart between the P channel transistor Q and the N channel transistor Q46. A switch P-channel transistor Q47 and an N-channel transistor Q48 are inserted in series, and the drain interconnection point of the switch transistors Q 1 and Q 2 is used as an output node.

Above 1. Each output node of the second clocked inverter 41, 42 is connected in common, and this output node has a
The first type uses the t source as an operating power source. A second CMOS inverter 12.13 is cascaded.

Then, each output of these two-stage inverters 12 and 13 is v
CMOS level shift circuit 1 using DD power supply as operating power supply
4, and on the output side of this level shift circuit 14, third and fourth CMOs whose operation power supply is the VIID power supply are connected.
S inverters 15 and 16 are connected in cascade.

In the above level converter, the selection signals M and M are @Q
#, @l#, the first clocked inverter 41
is selected. This first clocked inverter 41 has the same function as the first stage inverter 11 in the level converter shown in FIG. Also, contrary to the above,
Selection signals M and M are “1#”.

When @O#, the second clocked inverter 42 is selected and can be driven by CMOS level input.

FIG. 5 shows a level converter according to still another embodiment, and compared to the level converter shown in FIG.
The power supply node is connected to the first . The second clocked inverter %11-41.42 and the first. It is connected to each power supply node of the second CMOS inverter 12 and 13, and the dart of this transistor Q51 is
The difference is that it is connected to the DD power supply node and its substrate bias is set to the same potential as the source, but other parts are the same and are designated by the same reference numerals as in FIG.

The level converter shown in FIG. 5 has all the advantages described in the above embodiments, can select between driving by TTL level input and driving by CMOS level input, and can be used in a low voltage power supply system. ' Any one-way level conversion can be performed between the high-voltage power system and the high-voltage power supply system.

Note that the first-stage clocked inverters 41 and 42 in the above embodiment can be modified as shown in FIGS. 6 to 8, respectively. That is, in FIG. 6,
The load resistor RL in FIG. 5 is formed by a P-channel transistor Ql whose gate is grounded, and in FIG. ．Q
In FIG. 8, the load resistor 9 in FIG. 7 is formed by a P-channel transistor Q81 whose dot is grounded.

[Effect of the invention] As described above, according to the level converter of the present invention, T
Even when driven by TL level input, it is possible to convert to CMOS level without increasing the through current or increasing the transfer time). Effects such as easy provision of a bidirectional interface function for performing level conversion in any one direction can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the level converter of the present invention, Fig. 2 is a circuit diagram showing an extracted CMOS inverter in Fig. 1, and Figs. 3 to 5 are respectively other embodiments. FIGS. 6 to 8 are circuit diagrams showing modifications of the first-stage inverter in FIG. 5, and FIG. 9 is a circuit diagram showing a conventional level converter. 11.41.42...First stage inverter, 14...C
MOS level shift circuit, RL...load resistance, Ql,
. Ql21 q4. t Q42 j Q45 # Q
46°-CMOS inverter transistor, Q
, Q , Q , Q ... switch transistor, Q , Q ... N channel transistor. Applicant's representative Patent attorney Takehiko Suzue Figure 6Vcc 051~~RL Simple M~Q47 N~Q6 Figure 8Figure 7

Claims (3)

[Claims] (1) A first-stage inverter having a load resistor and a CMOS inverter connected in series between a first power supply node having a first power supply voltage and a ground terminal, and a second power supply provided after the first-stage inverter. C whose operating power is voltage
A level converter characterized in that a MOS level shift circuit and a MOS level shift circuit are formed on the same semiconductor chip. (2) An N-channel transistor whose gate is supplied with the second power supply voltage and whose substrate bias is set to the same potential as the source is inserted between the first power supply node and one end of the load resistor of the first stage inverter. The level converter according to claim 1, characterized in that: (3) The first stage inverter is connected in parallel to a first clocked inverter in which a switching MOS transistor is connected in series to a CMOS inverter between the load resistor and the ground terminal, and the first clocked inverter is connected in parallel to the first clocked inverter. and a second clocked inverter in which a switching MOS transistor is connected in series to a CMOS inverter, the input nodes and output nodes of the two clocked inverters are commonly connected, According to claim 1 or 2, the clocked inverters are switch-controlled so that the respective switching MOS transistors are selectively activated by a selection signal. level converter.