JPS6316341A - Microprogram control system - Google Patents

Abstract

PURPOSE:To operate the resources stored in a processor from the outside of the processor by shifting the control to a special processing routine when the coincidence is secured between the address outputted from a sequencer and the information stored in a register. CONSTITUTION:An address is set to a break point address holding register 118 and a processor 100 starts its normal processing. The addresses sent from a sequencer 109 are supplied to a control memory 104 and a comparator 120 via an address signal line 112. The comparator 120 compares the contents of the register 118 with the address set on the line 112. When no coincidence is obtained from this comparison, the address outputted from the sequencer 109 is supplied to the memory 104. While the head address of a monitor is supplied to the memory 104 when the coincidence is obtained from said comparison. Then the monitor is started and a series of processes of the processor 100 are broken by a held break point.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprogram control system for an information processing device, and more particularly to a method for realizing breakpoints in a microprogram as a method for debugging the microprogram. .

2. Description of the Related Art In recent years, microprogram control methods have been widely used as control methods for information processing devices. The characteristics of the microprogram control method are that the design and manufacture of the control section of an information processing device can be carried out systematically, which shortens the design period and makes maintenance easier; that it can easily realize complex functions; Examples include the fact that it is easy to add or delete elements that realize a function at the design stage. However, even in the microprogram control method, in order to realize complex functions, multi-step microprograms and microinstructions that control hardware in a complicated manner are still required.

FIG. 6 is a diagram showing a control part of a conventional microprogram control system. The microprocessor 600 includes a control unit (t6 old), a decoder 602 that receives a control signal 604, decodes the microinstruction code from the control memory 601, and outputs a microorder 603, and a control signal from the decoder 602. 606 and a microaddress sequencer 605 that outputs addresses to control store 601 via address signal path 608 under the control of control signals 607 from a macroinstruction decoder (not shown) of processor 600.

Problems to be Solved by the Invention In the microprogram control method of the conventional microprocessor configured as described above, it can only be accessed from the microprogram control hardware or the microprogram. Regarding various resources such as registers, the execution effect of a certain macroinstruction at an arbitrary address in the microprogram can be read out from the microprocessor, and the various resources that can only be accessed from the microprogram can be read out from the microprocessor. It was impossible to operate it from the outside.

Therefore, when a malfunction in a microprocessor's macro instruction is detected, it is difficult to determine whether the malfunction is a malfunction in the microprogram for the macro instruction or in the hardware that the microprogram accesses. .

In particular, the functions required of information processing equipment are becoming more sophisticated.
As microprograms become more complex, advanced and complex functions are required of microprograms, so it is important to strengthen the debugging function of microprograms in order to realize advanced information processing devices.

Means for Solving the Problems A microprogram control system for solving the above problems includes a control memory, a decoder that receives the output from the control memory, and a sequencer that outputs addresses under the control of the decoder. , an address conversion means for inputting an address output from the sequencer and outputting an address to the control memory, a register, a means for storing information in the register, and a means for manually converting the output of the register and the output of the sequencer. In a processor having means for detecting a match between the two, when the means for detecting a match detects that the address output from the sequencer and the information stored in the register match, The present invention is characterized in that an address conversion means is controlled to convert an address and output a special address to the control memory, thereby transferring control to a special processing routine provided in the control memory.

Embodiment FIG. 1 is a diagram showing an embodiment of a processor for executing the microprogram control method of the present invention. A processor 100 embodying the present invention exchanges information with a console 102 from its interface unit 103 via a system bus of an information processing system configured mainly around the processor 100. A part of the interface unit 103 is inside the processor 100 and the rest is outside the processor 100.

Each block shown inside the processor 100 shows only the control portion of the processor 100. The control memory receives the output from the address converter 105 and outputs information to the microinstruction decoder 106. Decoder 106 decodes the output from control memory 104 and the control signal 107 from other parts (not shown) of processor 100 and outputs micro-order 108 . Microaddress sequencer 109 outputs microaddresses on microaddress signal path 112. When a branch instruction is decoded by the decoder 106, information for generating a branch destination address is supplied to the sequencer 109 via an information path 111. Further, information for generating a microaddress for the next macroinstruction is supplied to the sequencer 109 via a signal path 110 from a microinstruction decoder (not shown).

Next, the /%-ware necessary for setting breakpoints will be explained. The set/reset flip-flop (abbreviated as SR-FF) 113 has a set input signal 11.
4 and reset human power word 115 can be done manually. This 5R-
FF113 is a break mode F that outputs a signal indicating whether or not to perform a break point to a signal path 116.
It is F. S R7F F1130 Set and reset will be described later.

The data in the interface section 103 is transmitted to the processor 100.
The break point address is stored in the break point address holding register 118 via the data bus 117 of the break point address.

This data is input to comparator 120 through output signal path 119 of register 118. Address signal path 112 is connected to the other input of comparator 120.

The comparator 120 outputs a logic value "1" as the output signal 121 when these two inputs match.

The AND gate 122 receives the output signal from the 5R-FF 113 and the output signal from the comparator 120 . 5R-FF
The output of 113 and the output of comparator 120 are both logic case 1.
', the logic value ``1'' (high level) is applied to the signal path 123.
Output. A signal on the signal path 123 at a certain time is a signal indicating that the address on the address signal path 112 at that time coincides with a breakpoint.

The signal on signal path 123 is input to a one clock delay element 124. As a result, a change in the signal on signal path 123 is transmitted to signal path 125 one clock later.

Signal path 125 connects to address translator 105.

The signal on the signal path 123 is processed by the delay element 124 to
The reason why the output of the address converter 105 is changed by the signal on the signal path 125, which is a delayed signal, is that after the microinstruction at the break point is executed, the address to the control memory 104 is switched and the control is executed. It's for changing.

When the signal on signal path 123 is a logic edge '0', that is, break mode is not set, or even if break mode is set, the address on address signal path 112 coincides with the break point. When it is not done,
The address converter 105 supplies the control memory 104 with the address output from the sequencer 109 at the next clock as it is. The signal on signal path 123 is a logical value.”
1'', that is, when the break mode is set and the address on the address signal path 112 matches the break point, the address converter 105 sends the address output by the sequencer 109 at the next clock to the control memory 104. The control is changed by outputting a predetermined address to the control memory without supplying the address.

FIG. 2 shows one embodiment of the address translator 105.

When the processor 100 is a microprocessor and the output of the sequencer 109 adopts a dynamic bus method, the characteristics of the dynamic bus are used to send the output from the sequencer 109 to the control memory 104 using the selection signal 125. It is possible to supply a specific address independently of the output of Control signal 12 of address converter 105
If one bit of the input of the control memory 104 is at a high level at the particular address when the bit of the input of the control memory 104 is at a high level, use the method shown in FIG. If the address is at low level, use FIG.

First, FIG. 2(a) will be explained.

A signal path 200 for one bit among the address signal paths to the control memory 104 is connected to the power supply 201 via a pass control transistor 203. Pass control transistor 203 is conductive when the control signal on signal path 204 is at a low level, and is turned off when the control signal on signal path 204 is at a high level. Also,
Signal path 200 is connected to ground 202 via series-connected pass control transistors 205, 207. The pass control transistor 205 is conductive when the control signal on the signal path 211 is at a low level, and is turned off when the control signal is at a high level. The pass control transistor 207 is conductive when the control signal on the signal path 208 is at a high level;
When it is at low/° level, it is in the cut-off state. Signal path 208
The upper control signal is the output of AND gate 220 and is determined by the control signals on signal path 209 and signal path 210.

The control signal on the signal path 208 goes high because the control signal on the signal path 209 goes high and the signal path 21 goes high.
Only when the control signal on 0 is low level, and in the case of combinations other than the above, it is low level. Signal path 204
is a signal obtained by inverting one of the two-phase clocks, for example, P
HII is connected to the signal path 209, and PHI2 is connected to the PHII of the signal path 204. One bit of the output from the control memory 104 is connected to the signal path 210.
1 is connected to a signal path 125.

The operation of the circuit shown in FIG. 2(a) will now be explained. First, consider the case where the signal on signal path 211 is at a low level.

In this case, pass control transistor 205 is in a conductive state. During the high period of the PHII clock, the pass control transistor 203 is in a conductive state, and the pass control transistor 2
07 is in the cutoff state, the signal path 200 is pre-charged. Next, during the high period of the PHI2 clock, the pass control transistor 203 is in a cut-off state, but when the 1-bit signal of the output of the control memory 104 on the signal path 210 is at a low level, that is, the logic current is "0", the signal is The control signal on path 208 goes high and pass control transistor 207 becomes conductive, and the charge on signal path 200 that was pre-charged during the high period of PHII is transferred to conductive pass control transistors 205 and 207. and is pulled to ground 202, causing signal path 200 to be at a low level or logic value '0'.

Furthermore, when the 1-bit signal output from the control memory 104 on the signal path 210 is at a high level, that is, has a logical value of '1' during the high period of the PHI2 clock, the pass control transistors 203 and 207 are in a cut-off state, so that the PH11 goes high. The charge on the signal path 200 that has been charged during this period is retained, so the signal path 200 becomes a high level, that is, a logical value.
1'.

Now consider the case where the signal on signal path 211 is at a high level. In this case, the pass control transistor 205
is in a cut-off state, so the value of signal path 210 causes PH
Whether the high period pass control transistor 207 of I2 is in the conductive state or in the cut-off state, the signal path 200 is PHI.
It is held at a high level during the high period of 2. In other words, whether the sequencer 109 outputs "0°" or "1" to a certain bit of the address signal 112, the signal path 211
is at a high level, the address input 200 to the control store 104 implementing FIG. 2(a) is forced to '1'.

Next, Section 211(b) will be explained.

A signal path 212 for one bit among the address signal paths to the control memory 104 is connected to the power supply 201 via a pass control transistor 203. Pass control transistor 203 is conductive when the control signal on signal path 204 is at a low level, and is turned off when the control signal on signal path 204 is at a high level. Also,
Signal path 212 is connected to ground 202 via parallel-connected pass control transistors 205, 207. The pass control transistor 205 is conductive when the control signal on the signal path 211 is at a low level, and is turned off when the control signal is at a high level. The pass control transistor 207 is conductive when the control signal on the signal path 208 is at a high level;
When it is at low level, it is in the cut-off state. The control signal on signal path 208 is the output of AND gate 220 and is determined by the control signals on signal path 209 and signal path 210. The control signal on signal path 208 is high only when the control signal on signal path 209 is high and the control signal on signal path 210 is low; in other combinations, , is low level. The pass control transistor 213 is conductive when the control signal on the signal path 206 is at a high level, and is turned off when the control signal is at a low level.

A signal obtained by inverting one of the two-phase clocks, for example 1fPH11, is connected to the signal path 204, and PH12 is connected to the signal path 209i and the lt signal path 204(7) PHI1.

One bit of the output from control memory 104 is connected to signal path 210, and signal path 125 is connected to signal path 211.

When signal path 211 is low, signal W82
06 Calorue level and pass control transistor 213
is in a cutoff state, and the charge on the signal path 212 is controlled only by turning on/off the pass control transistor 207. When signal path 211 is high, signal path 2
06 becomes high level only during the high period of PHI2, the pass control transistor 213 becomes conductive, and the signal path 2
12 is grounded regardless of whether the pass control transistor 207 is turned on or off, so during the high period of PHI2, the signal path 21
2 has a low level, that is, a logic value "0" (i.e., in FIG. 2), when the signal path 211 is at the 1 level, the sequencer 109 sets the
Whether 0' is output to a certain bit or 1' is output, the address input 212 to the control memory 104 is forcibly set to '0'.

The operation has been explained above with respect to FIGS. 2(a) and 2). For all bits in the output from control memory 104, FIG.
By applying either a) or b), the address converter 10
5 outputs a specific address when the control signal 125 shows a logical value of '1°, and when the control signal 125 shows a logical value of '0', outputs the address that the sequencer 109 outputs on the signal device 112 and stores it in the control memory. 104, even if there is only one address input to the address converter 105 and only one selection signal, the address converter 105
can output two types of addresses. Part 1
One is the address from the sequencer 109, and the other is the specific one fixed address.

A second address converter 105 is provided on the address signal path 112 between the sequencer 109 and the control memory 104.
By using the circuit shown in the figure, one of the address signal paths 112
One pass control transistor for each bit is the hardware for the multiplexer.

However, since control transistors are usually very easy to implement in LSI, the increase in hardware for multiplexers can be minimized.

FIG. 3 is a conceptual diagram of the memory map of control memory 104. Reference numeral 301 indicates an address at the time of reset, which is output to the address signal path 112 when the sequencer 109 is initialized when the processor 100 is reset, and 311 indicates an initialization routine that performs initialization processing inside the processor 100 immediately after reset. 302 is an address where you want to break for debugging. 303 is the start address of a monitor routine 313 that communicates between the inside of the processor 100 and the console 102 outside the processor.

Generally, one microinstruction is written within one word length output by the control memory by one microaddress. One microinstruction in the microprogram control system according to the present invention is one microinstruction.
The address is written within one word length output by the control memory. Therefore, changing one microaddress can completely change one microinstruction.

Breaks according to the present invention are monitored by the address converter 105 outputting the start address 303 of the monitor 313 as the next address of the break point to the control memory 104 instead of the address issued by the sequencer 109 at the break point. This is done by activating 313. On the monitor 313, the first address is 30.
3, a branch instruction to the address next to the first address 3030 is written. Next, the contents of the register 118 are saved as a return address generation address required when the monitor 313 returns to normal processing of the microprogram of the processor 100, and '
%- After saving the information stored in the software immediately before, the processor 100
It communicates with the external console 102. console 1
02, the monitor 313 writes the saved information back to the original hardware, and finally writes the microprogram of the processor 100 based on the saved contents of the register 118. A return address to normal processing is generated, the return address is given to sequencer 109, and control is returned to normal processing.

A branch microinstruction to the next address of the start address 303 is written at the start address 303 of the monitor 313 (for the following reason. Namely, after the microinstruction at the break point address 302 is executed, The address converter 105 inputs the address of the start address 303 of the monitor 313 to the control memory 104, but
This is because the sequencer 109 cannot output the address following the start address 303 of the monitor 313 by only inputting that address, and control cannot be transferred to the monitor 313.

By writing a branch microinstruction to the next address of the start address 303 in the start address 303 of the monitor 313, the address converter 105 sends the control memory 104 to the start address 303 of the monitor 313 at break time.
3 is supplied. Then, the control memory 104 outputs a branch microinstruction to the address next to the start address 303 to the decoder 106 . After the decoder 106 decodes the branch microinstruction, the decoder 106 controls the sequencer to sequentially output addresses from the address following the first address 303 (sends the snowy road 111). It becomes possible to transfer the information to the monitor 313, that is, to start the monitor.

An example of a method for communicating between the processor 100 and the console 102 using the monitor 313 will now be described.

The contents of the communication between the console 102 and the monitor 313 include setting and resetting the break mode, breakpoints and
address, processor 100 reading to console 102
address of register 118 in processor 100, address and data written from console 102 to register 118 in processor 100, return to normal processing from monitor 313.
It is a kind. Monitor 313 identifies the five types of communications based on command words from console 102.

An example of the rules for communication between the monitor 313 and the console 102 is shown in FIGS. 4 and 5. FIG. 4 shows the sequence of communication between the monitor 313 and the console 102, and FIG. 5 shows the sequence on the monitor 313 based on the communication rules on the console 102 side.

When the monitor 313 enters the communication state with the console 102, it first waits for a command from the console 102, and when it receives one of the five types of commands mentioned above from the console 102, it transfers control to the processing procedure according to the received command. .

The inside of the monitor 313 is roughly divided into three parts. First, the first step is to save the contents of the hardware resources used within the monitor 313. If the contents of the hardware resources determined at the broken address are destroyed due to processing by the monitor 313, the information to be destroyed is saved at the first stage of the monitor 313, and the information is saved at the last stage of the monitor 313. By restoring the saved information to the original hardware resources, the processing of the monitor 313 is prevented from leaving any influence on the subsequent processing of the processor 100.

The second stage of monitor 313 is communication with console 102 external to processor 100. The normal processing of the processor 100 is broken at a predetermined break point and control is transferred to the monitor 313.
The validity of the microprogram can be evaluated by reading out the values of the registers, status, etc. determined at the address broken by 3 to the outside of the processor 100 through communication with the console 102.

Further, debugging is possible by setting data to a register or the like using the monitor 313 from the console 102.

The third stage of the monitor 313 is to restore the evacuated data,
This is a return to normal processing from the monitor 313.

Returning from the monitor 313 means returning to the address next to the address from which control was transferred to the monitor 313.

In the present invention, the address 302 to which control is transferred to the monitor 313
register 118 immediately after transferring control to monitor 313
The monitor 313 can recognize it because it is saved in the first process of the monitor 313. Therefore, a branch microinstruction to the address 302 plus 1, that is, the next address after address 302, is placed at the final address of the monitor 313, and by executing that branch microinstruction, the monitor 313 returns to normal processing. will be done.

In the initialization routine 311, each part in the processor 100 is initialized normally, but the initialization of the newly provided hardware for breaking according to the present invention is performed by a reset signal to the entire processor 100. Do it on purpose. The activated reset signal resets the branch mode 5R-FF 113, and at the same time sets a known specific value in the break point address holding register 118. The initialization routine 311 is activated by the reset signal, and the moniker 313 is called once in the initialization routine. The monitor 313 is called in the initialization routine to communicate with the console 102, and for example, sets a break mode and sets a break point.

That is, the monitor 313 is run at the initialization stage immediately after reset and at a break point.

Next, the break operation will be explained with reference to the hardware configuration shown in FIG. 1 and the initialization routine and monitor provided in the control memory 104 shown in FIG.

The address converter 105 has a selection signal 125 of logical value '1'.
', regardless of the output from the sequencer 109, the start address 30 of the monitor 313 is stored in the control memory 104.
Designed to output 3.

First, a break operation is initiated within an initialization routine initiated by a reset signal to processor 100.

Break mode is set by communication with the outside of the processor at monitor 313. Next, an address is set in the break point address holding register 118 to cause a break at address 302, and the processor 100 starts normal processing in response to a return command. Addresses sent out one after another from sequencer 109 are supplied via address signal path 112 to control store 104 and comparator 120. Comparator 120 compares the contents of register 118 with the address on address signal path 112. When the two do not match, a logic value '0' is output on the signal path 121. As a result, the selection signal path 125 of the address converter 105
In the above case, the logical value becomes "0" with a delay of one clock, so the address outputted from the sequencer 109 is manually entered into the control memory 104 via the address converter 105.

In comparator 120, when the address on address signal path 112 matches the contents of register 118, signal path 12
Logic value “1” is output on 1.Break mode 5
Since R-FF113 is already set, signal path 1
If logic 1 '1'' is output on signal path 123
The upper value is a logical value of °1. After a one clock delay from the change in the signal on signal path 123, the signal on signal path 125 becomes a logical value '1'', and address converter 105 converts the signal to control memory 1.
By supplying the start address 303 of the monitor 313 to 04 and activating the monitor 313, a series of processing up to the address corresponding to the break point of the processor 100 is broken using the held break point.

The first step of the monitor 313 is to save the break point address stored in the register 118 to generate a return address and save various information, and the second step is to communicate inside the processor 100 with the console 102. When reading the contents of the registers to the console 102, manipulating the internal registers of the processor 100 from the console 102, setting the break mode, resetting the break point, and resetting the break points, a return command from the console 102 returns the monitor to the console 102. The third stage of 313 is the restoration of the various information that was saved, the generation of a return address based on the contents of the register 118 that was saved to generate the return address, and the branch microprocessor to the return address. By executing the instruction, the normal processing of the processor 100 can be resumed from the address following the broken address.

In other words, according to the present invention, break points can be set in a microprogram from outside the processor 100 using the monitor 313, and the break hardware allows a series of microprograms to be set after executing the microinstruction at the break point. It becomes possible to break the processing and transfer control to the monitor 313. monitor 313
Since the various cost sources within the processor 100 can be directly manipulated, it is also possible to know the internal state of the processor 100, so that the microprogram of the processor 100 can be debugged.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides break hardware and special processing routines such as the monitor 313 in the control memory of a processor, so that a series of microprograms can be stopped after execution of a microinstruction with a breakpoint. Processing can be interrupted and control transferred to a special processing routine. By using this special routine to break a series of microprograms and communicating with the outside of the processor, the processor's internal resources at the break point can be manipulated from outside the processor, making it easier to debug the processor's microprograms. This has the effect of making it possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing one embodiment of the address converter 105 shown in FIG. 1, and FIG. These are conceptual diagrams. FIG. 4 shows the communication sequence between the monitor 313 and the console 102, FIG. 5 shows the communication sequence between the console 102 and the monitor 313, and FIG. 6 shows the communication sequence required for the conventional microprogram control method. FIG. (Main reference number) 100... Processor implementing the present invention, 101...
・System bus of the information system 1 [1 system configured around the processor 100, 102...Consonobe 103...Interface section for exchanging information between the console 102 and the processor 100, i04...Control memory, 105・Address converter,
106...Microinstruction decoder, 107...Manual control signal for decoder 106, 10
8. Output signal from decoder 106, 109. Micro address sequencer, 110. Control signal input to micro address sequencer, 111. Control signal input from decoder 106 to sequencer, 112. Micro・Address signal path, 113...set/reset flip-flop (SR-FF), 114...5R-FF113 set control signal input, 1
15...5R-FF113 reset control signal input, 1
16... Output of 5R-FF 113, 117... Internal data bus of processor 100, 118
...Break point address holding register, 119...Output signal path from register 118, 120.
-Comparator, 121... Match signal output of comparator 120, 122...5
AND gate whose inputs are the output 116 of R-FF 113 and the match signal output 121 of comparator 120, 123...Output of AND gate 122, 124...1 clock delay element, 125...Address converter 1050 control input , 200・
・1 bit of the output of the address converter 105, 201...
Power supply, 202...Grounding, 204...Control signal for pass control transistor 203 based on clock signal, 205...Pass control transistor, 206...Control signal for pass control transistor 213, 2
07...pass control transistor, 208...control signal of pass control transistor 207, 2
09...Clock signal with opposite phase to 204, 210...1 bit in the address signal path 112, 211...address converter 1050 control signal, 212...1 bit of the output of address converter 105, 213... - Passage control transistor, 220, 221... AND gate, 301... Start address of initialization routine 311, 302... Address to break, 303... Start address of monitor 313, 311... Initialization routine, 313. - Monitor routine, 600... Processor, 601... Control memory, 60
2.' Decoder, 603... Micro order generated by decoder 602, 604... Control signal input to decoder 602, 60
5...Micro address sequencer, 606...Control signal input from decoder 602 to sequencer 605,

Claims (1)

[Claims] A processor that includes a control memory, a decoder that receives an output from the control memory, and a sequencer that outputs an address under the control of the decoder, wherein the processor receives the address output from the sequencer and performs the control. an address conversion means for outputting an address to a memory, a register, and a means for storing information in the register;
It further includes means for inputting the output of the register and the output of the sequencer and detecting a match between the two, and the means for detecting the match is configured to input the address output from the sequencer and the information stored in the register. If a match is detected, the address conversion means is controlled to convert the address, and a special address is output to the control memory, thereby controlling a special processing routine provided in the control memory. A microprogram control method characterized by transfer.