JPS63161594A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress the power supply voltage drop and the effect of noise onto an internal circuit by decreasing the peak current in the precharge period in a precharge circuit for a bit line. CONSTITUTION:Both transistors (TRs) P01, P02 having a small gm (mutual conductance) on one hand and TRs P11, P12 having a large gm on the other hand are connected in parallel between a power supply potential and each bit line in order to precharge the bit line to a power supply potential or a potential close thereto during the precharge period of the bit line. Then the timing to turn on both the TRs has a difference, the TRs P01, P02 with the small gm are turned on first to start precharge and then the TRs P11, P12 having the large gm are turned on to apply precharging. Thus, the peak value of the precharge current during the precharge period is reduced remarkably and the power supply voltage drop and the effect of power noise onto the internal circuit are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is mainly applied to metal-insulating film-semiconductor (hereinafter referred to as MIS)
The present invention relates to a semiconductor memory device using transistors, and particularly to a precharge circuit thereof.

BACKGROUND OF THE INVENTION FIG. 3 shows a precharge circuit for a semiconductor memory. ``P3 is a precharge signal of the bit line precharge circuit, P3゜, P31.P32 are P channel type MOS transistors, transistor P3゜ works to equalize the potential of bit lines B, B, and transistor P
3. - P3□ works to charge the bit lines B and B to the power supply potential or a potential close to it. W3 is a word line for a certain memory cell M.

FIG. 4 shows the input voltage waveform of the precharge signal "P3" input to the precharge circuit shown in FIG. 3 and the precharge current IPc during the precharge period. Signal “Ps”
When the bit line B@B is at L” (low) level, the bit line B@B is at the power supply potential (
VDD).

Problems to be Solved by the Invention In FIG. 3, when the precharge signals 3 and 3 are low, transistors P3 and P311 and P32 are in the on state. In addition to equalizing the potentials of the bit lines B and B, the power supply potential is It can be seen that the bit line is charged to a potential close to VDD.

At this time, precharge current! As shown in FIG. 4, the current waveform of the PC increases rapidly with the start of precharging during the precharging period, and has a very steep peak. Therefore, the instantaneous current value during precharging becomes a much larger value than the average current at a certain timing during the precharging period. In the case of a precharge circuit as shown in Fig. 3, the more bit lines are precharged by the precharge signal Ps, the more the peak current of the si-recharge current PC increases due to simultaneous precharging. The number will be added by the number of books. For example, the peak precharge current value for each pair of bit lines B and H is 1. If it is smA, this is 1
When precharging 00 lines at the same time, an instantaneous precharge current of 160 mA flows, and the flow of such a large current causes noise in the operation of other circuits due to a drop or fluctuation in the potential of the stain source voltage VDD. becomes.

As a result, the operation of other circuits becomes unstable or malfunctions, and of course, the operating current increases. Furthermore, as a countermeasure to the increase in peak current during precharging by the precharge circuit shown in FIG.
This requires a significant increase in the size of the DD or ground (VSS) line, which means an increase in the area of the precharge circuit, which inevitably affects the chip area, etc. , and large capacity and
The increase in the peak current value during precharging in precharge circuits due to higher density has become an increasingly serious problem both in semiconductor memory circuit design and process.

The present invention makes it possible to reduce the peak current value during the precharge period in a bit line precharge circuit of a semiconductor memory, thereby suppressing the drop in power supply voltage and the influence of noise on the internal circuit, and reducing the circuit scale. It is relatively small and the increase in area is kept to a minimum, making it easy to implement.

Means for Solving the Problems The present invention provides a bit line precharge circuit for a semiconductor memory in which each bit line and power supply potential are precharged to a power supply potential or a potential close to the power supply potential during a bit line precharge period. A configuration in which both a transistor with a small qm (mutual conductance) and a transistor with a large qm are connected in parallel on one side and a transistor with a large qm on the other is connected between the A difference is established, and a small transistor of Kqm is first turned on to start precharging.

After that, by configuring a switch circuit that equalizes both potentials by turning on a transistor with a large qm,
It is characterized by precharging.

Effect The present invention makes it possible to significantly reduce the peak value of precharge current during the precharge period, which has been difficult to achieve with conventional precharge circuits, by the means shown above. This reduces the power supply voltage drop and the influence of power supply noise on internal circuits, making it possible to suppress malfunctions of other internal circuits. In addition, since the circuit configuration can be realized with almost no increase in the number of transistors compared to conventional circuits, it is possible to minimize the increase in the area of the precharge circuit, and the problem of increase in chip area is almost ignored. Furthermore, the circuit configuration itself has a relatively simple structure, and the operation is not complicated and can be easily realized.

Embodiment FIG. 1 shows a bit line precharge circuit showing a first embodiment of the present invention. Pol, P02. Pll.

Pl. , Po. is a P channel MO8) transistor,
Wl is a word line for a certain memory cell M, 3P0 is a precharge signal input to transistor P01 ``02'' Oo, and ``Pl'' is a precharge signal input to transistor P1.

This is the precharge signal input to P12.

FIG. 2 shows the input waveforms of the precharge signals 6P0 and 3P1 when the pair of bit lines B and B are precharged, and the instantaneous current waveform of the precharge current IpCI7) during the precharge period. As shown in FIG. 2, the precharge signals "Po and δP1 are first
When it is 0, it is L'' (low) level and this is the input P.
Channel transistor P01. P02. Po. turns on, and after a certain period of time, 1=1. When the precharge signal OP1 becomes L" (low) level, the transistors P11 and P12 to which it is input turn on, and both '6P0 and dPl become "L" until 1=12.
``Shibricharge continues to operate at the level.

Among the P-channel transistors that perform on-fist-off operation in response to the precharge signal "P O' 6P 1 shown here, Pol and P02 are transistors with a sufficient ratio of qm, and Pll and P12 are transistors with a sufficient ratio of qm. It is a thick transistor.As for the transistor P0°, the bit line pair B, B can be sufficiently equalized during the precharge period.
It is sufficient if it is m.

By inputting the precharge signal shown in FIG. 2 to the precharge circuit shown in FIG. precharging will start. but,
At this time, the precharge signal '6P is H'' (High)
Since the level of transistor P44. P1° remains off. Transistor P04. Although P02 is in the on state, since the qm of these transistors is sufficiently low, a considerable amount of time is required to charge the pits 1B and B to the power supply potential VDD, so the precharging progresses slowly and as a result, the second As can be seen from the waveform of one instantaneous current of the precharge current IPC in the figure, the peak current waveform has a gentle mountain shape, and it can be seen that the precharge peak current value at this time is suppressed to a considerably small value. Recognize. Next, 1=1. And the precharge signal stone P1 is also “L”
A sufficiently large transistor P11. P
1□ is also turned on. Since qm is sufficiently large, the potential of the bit line B.100 is rapidly charged to a state close to the power supply potential VDD by these transistors.

It can be seen from FIG. 2 that the instantaneous current wave of the precharge current IPC at this time has a steep peak waveform due to a rapid rise. However, since the bit line has already been charged to some extent during the precharge period 1=0 to 1=11, 1=1. As a result, the precharge peak current value of the steep peak waveform in the subsequent precharge period is considerably suppressed.

Therefore, during the precharge period from t = to to 1 = 12, the precharge current IPC has two peaks as an instantaneous current waveform, but the precharge peak current values are significantly reduced. It has become something that can be done.

Further, the set qm value of the transistor can be easily optimized so that the bit line can be sufficiently charged to near the power supply potential during a desired precharge period. Furthermore, although there is a precharge circuit in the embodiment of the present invention, it can be realized by a circuit configured with an n-channel MOS transistor or a P-channel or N-channel MIS transistor that operates in the same manner as the present circuit. You may.

Effects of the Invention As described above, according to the present invention, it is possible to significantly reduce the peak current value during the precharge period of the bit line precharge circuit, thereby reducing the power supply voltage during precharge. This makes it possible to reduce noise and reduce noise to other circuits, thereby making it possible to stabilize the operation of the internal circuits of the semiconductor memory device. Furthermore, compared to the conventional technology, the increase in the number of transistors can be suppressed to a minimum, and the increase in the area of the precharge circuit is small, so it can be realized by sufficiently suppressing the effect on the increase in the chip area. This is extremely effective in increasing the density and integration of semiconductor memory devices.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining the precharge operation of a semiconductor memory device in an embodiment of the present invention, FIG. 2 is a waveform diagram showing signal waveforms and current waveforms regarding the circuit of FIG. 1, and FIG. A circuit diagram for explaining a precharge operation of a conventional semiconductor memory device. FIG. 4 is a waveform diagram showing signal waveforms and current waveforms regarding the circuit of FIG. 3. Pll '12"00"011P02°, p channel MO8) transistor, 3P0...1st
precharge signal, 6P, . . . second precharge signal, Wl . . . word line, !・
... Precharge Electric PC"' style. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Map Ward Ward Q

! S Saddle C! 2 1 outside H

Claims (2)

[Claims] (1) As a transistor for each bit line provided to precharge the bit line to the power supply potential during the precharge period of the bit line of the semiconductor memory element, a transistor in which multiple transistors with different mutual conductances are connected in parallel is connected to the power supply and the bit line. The semiconductor memory device is configured to precharge the bit line by connecting between the bit lines and turning on the transistor with a small mutual conductance and the transistor with a large mutual conductance at different timings. (2) The semiconductor memory device according to claim 1, further comprising a switch circuit that equalizes a pair of bit lines during a period in which the bit lines are precharged.