JPS63160250A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63160250A JPS63160250A JP61307421A JP30742186A JPS63160250A JP S63160250 A JPS63160250 A JP S63160250A JP 61307421 A JP61307421 A JP 61307421A JP 30742186 A JP30742186 A JP 30742186A JP S63160250 A JPS63160250 A JP S63160250A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- film
- semiconductor device
- thickness
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000007747 plating Methods 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 6
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 4
- 239000008096 xylene Substances 0.000 claims description 4
- KOKPBCHLPVDQTK-UHFFFAOYSA-N 4-methoxy-4-methylpentan-2-one Chemical compound COC(C)(C)CC(C)=O KOKPBCHLPVDQTK-UHFFFAOYSA-N 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- -1 acrylyl Chemical group 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000004528 spin coating Methods 0.000 description 4
- 239000007921 spray Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- SVONRAPFKPVNKG-UHFFFAOYSA-N 2-ethoxyethyl acetate Chemical compound CCOCCOC(C)=O SVONRAPFKPVNKG-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にフォトレジ
ストめ膜厚増加によりＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａ
ｔｅｄ Ｂｏｎｄｉｎｇ） ・方式の半導体装置の金属
電極（金属バンブ）の高精度化、微細化を行うことがで
きる半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular, to increase the thickness of a photoresist film to improve TAB (Tape Automation).
The present invention relates to a method for manufacturing a semiconductor device that can improve the precision and miniaturize metal electrodes (metal bumps) of a semiconductor device using the ted bonding method.
従来のＴＡ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂ
ｏｎｄｉｎｇ）方式の半導体装置の製造方法として、例
えば、半導体基板上に形成した酸化膜および窒化膜の上
に所定のパターンのフォトレジストを設け、このフォト
レジストのパターン開口部にメッキ法によって（数μｍ
の高さの）金属バンプを形成する方法がある。Conventional TA B (Tape Automated B
For example, a photoresist with a predetermined pattern is provided on an oxide film and a nitride film formed on a semiconductor substrate, and a plating method (a few μm
There is a method of forming metal bumps (with a height of
フォトレジストの被着、方法は、ゴム系のネガレシスト
またはノボラック系のポジレジストの回転塗布、あるい
は、リストン等の貼付が行われている０回転塗布は通常
のＩＣ製造工程と同一で容易に実施できるという長所が
あり、リストン等の貼付は十分な膜厚が得られるという
長所がある。The photoresist application method is the same as the normal IC manufacturing process and can be easily performed by spin coating of rubber-based negative resist or novolac-based positive resist, or zero-turn coating in which Liston is pasted. It has the advantage that a sufficient film thickness can be obtained by pasting Liston and the like.
第２図は半導体基板ｌ、酸化膜２、窒化膜３．７’ ｉ
／ Ｐ を膜４を形成し、その上に前述したフォトレ
ジスト５を設け、その開口部にＴ ｉ ／ Ｐ を膜４
に通じる金属バンプエ６を設けた半導体装置を示してい
る。Figure 2 shows a semiconductor substrate l, an oxide film 2, a nitride film 3.7'i
A film 4 of T i /P is formed, the photoresist 5 described above is provided thereon, and a film 4 of T i /P is formed in the opening of the photoresist 5.
A semiconductor device is shown in which a metal bump 6 is provided leading to the semiconductor device.
〔発明が解決しようとする問題点コ
しかし、従来の半導体装置の製造方法によれば、回転塗
布で形成可能な第２図の７オトレジスト１５の膜厚は数
μ階が限度であるため、メッキの横広がりが（金属バン
プ１６の部分１６ａ）大きく、バンプピッチの微細化が
困難という不都合がある。[Problems to be Solved by the Invention] However, according to the conventional semiconductor device manufacturing method, the film thickness of the photoresist 15 shown in FIG. 2, which can be formed by spin coating, is limited to several μm. There is a disadvantage that the lateral spread (portion 16a of the metal bump 16) is large, making it difficult to miniaturize the bump pitch.
また、複数回の塗布により厚い膜を得ようとすると、膜
厚の均一性が劣化し、特に基板周辺部での盛り上がりの
ため十分なパターン形成が困難になり、微細なパターン
の形成が不可能になる。あわせて、工程数増加による生
産性の低下という不都合がある。In addition, if you try to obtain a thick film by applying it multiple times, the uniformity of the film thickness will deteriorate, and it will be difficult to form a sufficient pattern due to the swelling especially around the substrate, making it impossible to form a fine pattern. become. In addition, there is a disadvantage that productivity decreases due to an increase in the number of steps.
一方、リストン等の貼付による場合は、半導体基板への
貼付装置、貼付後の切断装置等の特殊な装置が新たに必
要であり、解像力が５０〜１００μｍ程度と低く、その
うえ、基板とフィルムの密着性が不十分になりがちとい
う不都合がある。On the other hand, when attaching a liston, etc., new special equipment is required such as an attaching device to the semiconductor substrate and a cutting device after attaching, the resolution is low at about 50 to 100 μm, and in addition, the adhesion between the substrate and the film is low. This has the disadvantage that it tends to be insufficiently sexual.
本発明は上記に鑑みてなされたものであり、工程数増加
や特殊な装置の導入なしに、メッキの横広がりを防止し
てバンプ寸法精度を高くし、バンプピッチの微細化がで
きる半導体装置を製造するため、半導体基板上に所定の
粘度に調整されたアクリル系フォトレジストを回転塗布
によって塗布してフォトレジスト膜厚を２０μｍ以上に
形成できるようにした半導体装置の製造方法を提供する
ものである。The present invention has been made in view of the above, and provides a semiconductor device that can prevent lateral spread of plating, increase bump dimensional accuracy, and miniaturize bump pitch without increasing the number of steps or introducing special equipment. To provide a method for manufacturing a semiconductor device, in which an acrylic photoresist adjusted to a predetermined viscosity is coated on a semiconductor substrate by spin coating to form a photoresist film thickness of 20 μm or more. .
以下、本発明の半導体装置の製造方法を詳細に説明する
。Hereinafter, the method for manufacturing a semiconductor device of the present invention will be explained in detail.
第１図は本発明の一実施例を示し、半導体基板１上にシ
リコン酸化膜２を形成し、その上にシリコン窒化膜３を
形成する。次に、前記シリコン窒化膜３にＴ ｉ ／
Ｐ を膜４で配線を形成した後、前記半導体基板１を約
１１００Ｏｒｐで回転させ、アクリル系フォトレジスト
をエチルセロ゛ソルブアセテートで約３０００ｃｐに粘
度調整したものを滴下してフォトレジストＭ５を形成す
る。これにより膜厚約２０ＩＪ１１、均−性成μｍ以内
の良好な膜が形成される。FIG. 1 shows an embodiment of the present invention, in which a silicon oxide film 2 is formed on a semiconductor substrate 1, and a silicon nitride film 3 is formed thereon. Next, the silicon nitride film 3 is coated with T i /
After wiring is formed using the P film 4, the semiconductor substrate 1 is rotated at about 1100 rpm, and an acrylic photoresist whose viscosity has been adjusted to about 3000 cp with ethyl cellosolve acetate is dropped to form a photoresist M5. As a result, a good film with a thickness of about 20 IJ11 and a uniformity of less than 1 μm is formed.
次に、前記半導体基板１を８０℃、窒素雰囲気で約２０
分間熱処理後、通常のフォトマクスを用いて露光する。Next, the semiconductor substrate 1 is heated at 80° C. in a nitrogen atmosphere for about 20 minutes.
After heat treatment for a minute, it is exposed using a normal photomax.
露光後、前記半導体基板上を１．１．１．ｌ−リクロル
エタン等に浸漬、あるいは、そのスプレー中に曝して現
像を行う。さらに、前記半導体基板１を８５℃１時間程
度熱処理して乾燥させた後、電解金メッキ法により１５
〜２０ｐｍの金バンプ６が形成される。本発明の実施例
では、メッキ厚がフォトレジスト厚以下であるため、第
２図に示す従来の半導体装置の製造方法による半導体装
置のようなメッキの横広がりがないことからバンプの高
精度化、バンプピッチの微細化が可能である。After exposure, the semiconductor substrate is subjected to 1.1.1. Development is carried out by immersion in l-lychloroethane or the like, or by exposing it to its spray. Furthermore, after heat-treating the semiconductor substrate 1 at 85° C. for about 1 hour and drying it, electrolytic gold plating is applied to the semiconductor substrate 1.
~20 pm gold bumps 6 are formed. In the embodiment of the present invention, since the plating thickness is less than the photoresist thickness, there is no lateral spread of the plating as in the semiconductor device produced by the conventional semiconductor device manufacturing method shown in FIG. It is possible to miniaturize the bump pitch.
本発明の第２の実施例として、前記フォトレジスト２の
現像において、前記半導体基板ｌを数１１００ｒｐで回
転させながらキシレン５０％、ペントキソン５０％の混
合液のスプレー中に数十秒〜数分曝し、さらにキシレン
のみのスプレー中に数１０秒間曝して現像及びリンスを
行うことによりパターンを形成する。As a second embodiment of the present invention, in developing the photoresist 2, the semiconductor substrate 1 is exposed to a spray of a mixed solution of 50% xylene and 50% pentoxone for several tens of seconds to several minutes while rotating at several 1100 rpm. Then, a pattern is formed by exposing the film to a spray of only xylene for several tens of seconds to perform development and rinsing.
第１の実施例と同様に前記半導体基板１に熱処理後、メ
ッキを施すことにより、第１の実施例と同様にメッキの
横広がりのない半導体装置を得ることができる。By plating the semiconductor substrate 1 after heat treatment in the same manner as in the first embodiment, it is possible to obtain a semiconductor device in which the plating does not spread laterally, as in the first embodiment.
以上説明した通り、本発明の半導体装置の製造方法によ
れば、半導体基板上に所定の粘度に調整されたアクリル
系フォトレジストを回転塗布によって塗布し、露光後、
有機塩素系溶剤またはキシレン及びペントキソンの混合
液を用いて現像し、熱処理後、メッキにより金属バンプ
を形成するようにしたため、工程数増加や特殊な装置の
導入なしにメッキの構法がりを防止して金属バンプの高
精度化、バンプピッチの微細化が可能になる。As explained above, according to the method for manufacturing a semiconductor device of the present invention, an acrylic photoresist adjusted to a predetermined viscosity is applied onto a semiconductor substrate by spin coating, and after exposure,
Development is done using an organic chlorine solvent or a mixture of xylene and pentoxone, and after heat treatment, metal bumps are formed by plating, which prevents the plating structure from changing without increasing the number of steps or introducing special equipment. It becomes possible to improve the precision of metal bumps and to miniaturize the bump pitch.
第１図はＴＡＢ方式の半導体装置に本発明を通用した実
施例を示す説明図。第２図は従来の半導体装置の製造方
法による半導体装置を示す説明図。
符号の説明
１−−−−−−一半導体基板
２−一一〜−−−シリコン酸化膜
３−・−シリコン窒化膜
４−−−一〜・−Ｔ ｉ ／ Ｐ を膜５・・−・−ア
クリル系フォトレジスト６．１６・−・・・金バンプFIG. 1 is an explanatory diagram showing an embodiment in which the present invention is applied to a TAB type semiconductor device. FIG. 2 is an explanatory diagram showing a semiconductor device manufactured by a conventional semiconductor device manufacturing method. Explanation of symbols 1 - - - Semiconductor substrate 2 - - - Silicon oxide film 3 - - Silicon nitride film 4 - - - - Ti / P film 5 - - - Acrylic photoresist 6.16 --- Gold bump
Claims (2)
てメッキ法によって金属電極を形成する半導体装置の製
造方法において、 所定の粘度に調整されたアクリル系フォトレジストを前
記半導体基板上に１５μｍ以上の厚さに被着する工程と
、 前記アクリル系フォトレジストを露光する工程と、 前記アクリル系フォトレジストを有機塩素系溶剤により
現像する工程と、 前記フォトレジストのパターン開口部にメッキ法により
金属電極を形成する工程を有することを特徴とする半導
体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a metal electrode is formed by plating through a photoresist provided on a semiconductor substrate, an acrylic photoresist adjusted to a predetermined viscosity is applied onto the semiconductor substrate in a thickness of 15 μm or more. a step of exposing the acrylic photoresist to light; a step of developing the acrylic photoresist with an organic chlorine solvent; and forming a metal electrode in the pattern opening of the photoresist by a plating method. 1. A method of manufacturing a semiconductor device, comprising a step of forming a semiconductor device.
混合溶液によって現像する特許請求の範囲第１項記載の
半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the developing step is performed using a mixed solution of xylene and pentoxone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61307421A JPS63160250A (en) | 1986-12-23 | 1986-12-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61307421A JPS63160250A (en) | 1986-12-23 | 1986-12-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63160250A true JPS63160250A (en) | 1988-07-04 |
Family
ID=17968854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61307421A Pending JPS63160250A (en) | 1986-12-23 | 1986-12-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63160250A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218281B1 (en) | 1997-12-26 | 2001-04-17 | Fujitsu Limited | Semiconductor device with flip chip bonding pads and manufacture thereof |
-
1986
- 1986-12-23 JP JP61307421A patent/JPS63160250A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218281B1 (en) | 1997-12-26 | 2001-04-17 | Fujitsu Limited | Semiconductor device with flip chip bonding pads and manufacture thereof |
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