JPS63158917A - Error correction method - Google Patents

Abstract

PURPOSE:To heighten the reliability of decode information, by correcting a prescribed number of errors less than the maximum number of errors possible to be corrected at a preceding and a succeeding encode, providing an error pointer on all of the correction blocks when the errors exceeding the prescribed number exist, and inspecting the reliability of an error position found from a syndrome at the time of decoding at the next stage with the pointer. CONSTITUTION:A first check word generated from a first information group and the second check word of a second information group separately from a group including the constituent word of the first information group are added and transmitted, and those are received and error-corrected by using the first and the second check words. At this time, in the preceding and succeeding decode which error-correct the second group by using the second check word, for example, when error correction is suppressed to the correction of one word even when it is possible to correct four words at maximum, and two or more erroneous words are detected in the decode, the pointers are attached on all of the words of error correction blocks, and the number of pointers at time of decoding at the succeeding stage is investigated, and the error indicated by a found error position is corrected if the number of pointers is within a prescribed value. By such constitution, it is possible to decode the information with high reliability.

Description

[Detailed description of the invention] : Industrial application field] This invention has high error correction ability for both burst errors and random errors, and reduces the risk of error detection being missed or incorrect correction occurring. related to error correction methods.

2. Summary of the Invention] In the first stage decoding, this invention corrects errors up to a predetermined number that does not reach the maximum number of errors, and when there are errors exceeding this predetermined number, all of the errors in the error correction block are corrected. A pointer indicating an error is set for the next stage of decoding, and the reliability of the error location determined by the error syndrome is checked using the error pointer set during the previous stage of decoding. ,
As a checking method, the reliability of decoded data is improved by referring to the number of error pointers.

[Conventional technology]

The applicant of the present application previously proposed a method called cross interleave as a data transmission method effective against burst errors. This generates a first check word sequence by supplying one word included in each of the PCM data sequences of a plurality of channels in a first arrangement state to a first error correction encoder; A second check word sequence is generated by placing the check, check word sequence, and the PCM data sequence of multiple channels in a second arrangement state, and supplying one word contained in each to a second error correction encoder. Double interleaving (arrangement rearrangement) is performed on a word-by-word basis. Interleaving involves transmitting the check words and PCM data included in a common error correction block in a distributed manner, and when returning them to the original arrangement on the receiving side, error words among multiple words included in the common error correction block are The aim is to reduce the number.

In other words, when a burst error occurs during transmission, this burst error can be dispersed.

If such interleaving is performed twice, the first and second
Since each of the check words constitutes a separate error correction block, even if one of the check words cannot correct an error, the other can be used to correct the error, thus reducing the error correction ability. can be further improved.

[Problem that the invention seeks to solve]

By the way, if even one bit in one word is erroneous, the entire l word is treated as erroneous, so when dealing with received data that has a relatively large number of random errors, it is not necessary to have sufficient error correction ability. I can't say it's enough.

This is an error correction code with high correction ability that can detect and correct up to a 2-word error in a predetermined word, for example, within one block, and if the error location is known, it can also correct more than 3-word errors or 4-word errors. (a type of adjacent (b-ad)cent code) can be improved by combining the above-mentioned multiple interleaving.

Moreover, this error correction code has a feature that the structure of the decoder can be made extremely simple when only one word error is to be corrected.

However, even if such an error correction code with high correction ability is used, there are the following problems.

That is, when first-stage decoding is performed on the second error correction block and then next-stage decoding is performed on the first error correction block, incorrect error detection (detection error) and erroneous correction occur in the first-stage decoding. This detection error and erroneous correction cause a new detection error in the next stage of decoding.
This becomes a factor in erroneous corrections, and the occurrence of these malfunctions as a whole becomes even stronger. Furthermore, as the number of error words to be corrected increases, the probability that the above-mentioned detection errors and erroneous corrections will occur generally increases.

[Means for solving simple problems]

In the present invention, during the previous stage decoding, even if a maximum of 4 word errors can be corrected with a code having a high error correction ability as described above, the correction is limited to, for example, 1 word error. At the same time, when the previous stage decoding detects that a word beyond that, that is, a word of two or more words, is incorrect, a pointer indicating the error is added to all words in that error correction block. , the number of pointers is checked in the subsequent decoding, and the error indicated by the error location obtained in the subsequent decoding is corrected if the number of pointers is within a predetermined value.

[Effect]

The reliability of the error location determined in the subsequent decoding is checked by the number of pointers set in the previous decoding, thereby preventing detection errors and erroneous corrections in the subsequent decoding.

Therefore, the risk of detection errors and erroneous corrections during error detection and correction is reduced.

〔Example〕

First, the error correction code used in this invention will be explained. When describing an error correction code, a vector representation or a cyclic group representation is used. First, consider an irreducible m-th order polynomial F (X) on G F (2). The irreducible polynomial F (X) has no roots on the field GF(2) in which only elements 0'' and 1 exist.

Therefore, consider a virtual root α that satisfies (F(x)=0). At this time, 21 expressed as a power of α including zero elements
different elements 0. α, α2. α3...α−1 constitutes an extended field GF (2”). GF (2”)
”) is an m-th order irreducible polynomial F (
is a polynomial ring modulo X). The element of G F (2”) is 1.α=(X).

α'= (X")...α'"-1=(xg"-1)
It can be expressed as a linear combination of That is, ao+a, (x)+a2(x”)↓・----;111
-, (X"-')=a, +a, α+a2α2+・
...+a, -1α''-1 or (all-1m a
ll-2"...a2+ a l+ aQ) Here, a
;,, a l” ” am-r E GF (2).

- As an example, consider G F (2”) (mad,
F (X) = x”+ x’+ x’+ x”+1)
All 8-bit data is a, X'+16X'+asX' +a, X' +a
3X30a2X"'-a,X +a.

or (a71 a6.as, a4. a,,, a2
+ aIn aO), so for example al
is assigned to the MSB side and ao to the LVB side. a, GF (2)! = belongs, so it is 0 or l.

Also, the following matrix T from polynomial F (X) to (mXm)
is guided.

Another representation uses cyclic groups.

This takes advantage of the fact that the 0 element is removed from G F (2') and the remaining elements form a multiplicative group of order 2"-1. The elements of G F (2') are transformed into a cyclic group. Expressed using 0, 1 (=α′-”), α, α2. α°・・・α
It becomes 2'-2.

Now, in one example of this invention, m bits are one word,
When one block is composed of n words, check words are generated based on the parity check matrix H shown below. Also, the parity check matrix H can be similarly expressed using the matrix T. can.

However, d is a unit matrix of (mxm).

As described above, the expression using the root α and the expression using the generator matrix T are similar to each other.

For example, in the case of using four (k=4) check words, the parity check matrix H is as follows. One block of received data is expressed as a column vector V = (W--1, W-
-2...” ” Wl, We) (However, Wl ==W
t+ei, et: error bang) Then, four syndromes S Os S + r occur on the receiving side.
Sas S3 becomes. This error correction code has the ability to correct errors up to 4 words. In other words, it is possible to detect and correct errors up to 2 words within one error correction block, and when the error location is known,
Correction of 3-word errors or 4-word errors is possible.

4 check words in 1 block (p = Ws.

q = W2. r = W, s = W(1) are included. This checkword can be obtained by solving the following four-dimensional simultaneous equations. However, Σ means le.

If a total of 7 processes are omitted and only the results are shown, it becomes. In this way, check 7 words p, q.

The role of the encoder provided on the transmitting side is to form r and s.

Next, a basic algorithm for error correction when data including the check code formed as described above is transmitted and received will be described.

[1] When there is no error: So”5I=S2=Ss=0
(2) In case of 1 word error (error pattern at error location 1 is ei): 5o=et
St=α'et S*=α"et Sa=α3'e
Therefore, when i is changed sequentially, it can be determined whether or not there is a one-word error based on whether this relationship holds true. Alternatively, it becomes 08I82, and the error location i can be found by referring to the conversion table previously stored in the ROM for the pattern of C1.

The syndrome So at that time is the error pattern eI
Become that.

[3] In case of 2-word error (ei, ej) Transforming the above equation, [α'(crj So+ St> = α'Sl”57α
'(aJS+ + 52> = α'S2; If 53 is established, it is determined that there is a 2-word error, and the error locations i and j are known. In other words, by changing the combination of l and J,
Check whether the above equation holds true. The error pattern at that time is C4〕37-)'z5- (et ei et)
In the case of: Transforming the above equation, we get a'(a'(α'so+s,)+(α'S,,S,))
If =αj(α's,+82)+(cr's2+s,) holds true, it can be determined that there is a 3-word error. However, (S(
1"FO1s++0, S240).Each error pattern at that time is determined by.In reality, the configuration for correcting a 3-word error becomes complicated, and the time required for the correction operation becomes longer. Therefore, it is practical to perform error correction calculations by combining the case where the error locations of i, j, k, j! are known by pointers and using the above equation for checking at that time.

(5) 47-do x 5-(et, eJ, ehs e
x ) (D case: [50=e1+ej+ek+e1! St 'CI' et + CI'ej"α'e
k) α'ex Transforming the above equation, the error location (t) is determined by the point.

J, k, j! If the error is known, error correction can be performed by the above-mentioned operation.

Note that if the number k of check words is further increased, the error correction ability is further improved. For example, if (k=6), it has error correction capability of up to 6 words. That is,
It can detect and correct up to 3 word errors, and when the error location is known, it can correct up to 6 word errors.

Next, a specific example in which the present invention is applied to recording and reproducing audio PCM signals will be described with reference to the drawings.

FIG. 1 shows the entirety of an error correction encoder provided in a recording system, and an audio PCM signal is supplied to its input side. The audio PCM signal has a sampling frequency f, (for example, 44
．． I CkHz)) and sampled with 1
It is formed by converting the sample into one word (16 bits in two's complement code). Therefore, for the left channel audio signal, (Lo, t
, 1. L2...) and a PC in which each word is consecutive
M data is obtained, and PCM data in which each word is consecutive (Ro, Rr, Ro...) is also obtained for the right channel audio signal. This left and right channel PCM data is divided into 6 channels each,
A total of 12 channels of PCM data series are input. At a predetermined timing, (L @h+ R@n+
'L @h-In R6n. ,.

L @hm2+ k+2. L@tl+1. Ll&+3s
12 words of L@R-4s R@h-@) are manually input. In this example, one word is divided into upper 8 bits and lower 8 bits, and 12 channels are further processed as 24 channels.

For simplicity, one word of PCM data is expressed as W, and the upper 8 bits are suffixed with W,, A and A, and the lower 8 bits are W,, B.
and B suffixes are added to distinguish them. For example, L
6. , is W+z, , , A and W1□9. It will be divided into two parts, B.

This 24-channel PCM data sequence is first supplied to an even-odd interleaver (1). (n=0, 1
．． 2...), then Ls-(= Wli-
,A.

W 121% I B ) % Rga
(= Wt 2a + t* A * W12
The1w B) %Lsn. 2 (=W12
R*4s A + Wtah+4w B ), R
Ga. 2(= Wl2., *S, A, Wla--
s, B), Lie. 4(=W12m+1A, Wt
2n, s, B), RIIR+14 (=w, 2n*l
1w A, Wl 2h*ll+B) are even-numbered words, and the other words are odd-numbered words. Each of the PCM data series consisting of even-numbered words is processed by a 1-word delay circuit (2 people) of an even-odd interleaver (1).
2B) (3^) (3B) (4A) (4B> (5
^) (5B) (6A) (6B) (7A) (7
B) is delayed by one word. Of course, more than one word, for example eight words, may be delayed.

In the even-odd interleaver (1), 12 data sequences consisting of even-numbered words occupy the first to twelfth transmission channels, and one data sequence consisting of odd-numbered words occupies the first to twelfth transmission channels.
The 10-even-odd interleaver (1), which converts two data sequences so that they occupy the 13th to 24th transmission channels, detects errors in two or more consecutive words for each of the left and right stereo signals. However, this is to prevent this error from becoming uncorrectable. For example (Ll-
Considering three consecutive words such as +, Lt, Lt, etc., if Ll is incorrect and this error cannot be corrected, it is desired that Ll-1 or LL,l is correct. When correcting incorrect data L1, Lt is interpolated using the previous correct word Li-1 (previous value hold), Ll-1 and L1+
This is to interpolate LL with an average value of 1. Even-odd interleaver (1) delay circuit (2A) (2B)
~(7A) (7B) are provided to ensure that adjacent words are included in different error correction blocks. Also, the reason why transmission channels are grouped for each data series consisting of even-numbered words and data series consisting of odd-numbered words is that when interleaving is performed, the recording of adjacent even-numbered words and odd-numbered words This is to make the distance between the positions as large as possible.

At the output of the even-odd interleaver (1), a PCM data sequence of 24 channels in the first arrangement state appears, and one word is extracted from each of them and supplied to the encoder (8), where it is checked by the first checker. Word Q12h+Q, 2R2l
, Q1211°2* Q12M** are formed. 1st
The first error correction block including the check word is (Wl2h-+2+ As W1211-1fb E
3SWun++-+2+ As WL2h+1-1b
BsW12R-4-12, As W1211+4-12
*13. lol... 5-12*As J2n*%
-H* BsWI2h*@-12+ ASW12h+l
-Be Bs WI2n+I-L2* As Wl1m
+9-To BsW12.42+ A SW +□7.
2+ Bs WIln+3+ As W12R-b
3* BsW l 211°6. A, W12. . @
*BSW+ 2h+ff+ As W12n*? y
Bswe2n. 1olA% Wl2h, 10eBS
W129-11+A1W12+s+1lJsQ City,
Q12n*l% q,,. 2. QI2T
h. 3). The first encoder (8) encodes the number of words in one block: (n=28), the number of bits in one word - (n=8), and the number of check words: (k=4). .

These 24 PCM data sequences and 4 checkword sequences are supplied to an interleaver (9).

The interleaver (9) changes the position of the transmission channel so that a check word sequence is interposed between the PCM data sequence consisting of even-numbered words and the PCM data sequence consisting of odd-numbered words, and then performs interleaving for interleaving. Delay processing is being performed. This delay processing
ID, 2D, 3D, 4D...2 for each of the other 27 transmission channels excluding the th transmission channel.
This is done by inserting a delay circuit with a delay amount of 6D, 27D (where D is a unit delay amount, for example, 4 words).

At the output of the interleaver (9), 28 data sequences in the second constellation state appear, one word is extracted from each data sequence and supplied to the encoder (lO), and the second Check word P 12n+P 12h*
le P l 2h. 2. P 121143 is formed. The second error correction block consisting of 32 words including the second check word is as follows.

(Wl 211-12AsVb 211-1 i (i
1) IBW + 2++m1-1 a (211-1
)mnWlZa,,-1□(,.1-111B%W+
mho4-1! (41141) lA%W+ 2.1
+4-12 (Il+-11, B'W'Vl awes
-12tso-o, A, Wl Rh+8-12tq
o-+> +BQ1211-...12111, Q1
2R-1-12 (lcoD) 嘱q、、TI-ト1N1
Kazu If) s Q12R◆Ko 12 (IID)
%W+2++th+o-+ 2 <tea)AWL i
+1+ l a-+ t n5a), B, wl mho
l 1-1 i (18D) AWL 2h*l +
-1x <xlo)+BP tie~ P 12
11-I SP 12R+2 s P +211
-3) containing such first and second check words.
Among the two data streams, an interleaver (11) in which a one-word delay circuit is inserted is provided for the even-numbered transmission channel, and an inverter (12) is provided for the second check word series. ) (13)(14)
(15) is inserted. The interleaver (11) takes care of the fact that an error that spans the boundary between blocks is likely to result in an uncorrectable word count error. Additionally, inverters (12) to (15) are provided to prevent malfunctions in which all data in one block becomes "0" due to dropout during transmission, and the reproduction system determines this as correct data. ing.

An inverter may also be inserted for the first checkword series for the same purpose.

Then, 3
Each two words are serialized, and as shown in FIG. 2, a 16-bit synchronization signal is added to the beginning of each word to form one transmission block and then transmitted. In FIG. 2, for simplicity of illustration, one word extracted from the first transmission channel is shown as U. Specific examples of transmission systems include magnetic recording and reproducing devices, rotating disk devices, and the like.

The above-mentioned encoder (8) relates to the error correction code as described above, (n=28. m =8. k=4)
and a similar encoder (10) is (n=32. m
=3. = 4).

The reproduced data is added to the error correction decoder shown in FIG. 3 every 32 words of one transmission block. Since this is playback data, it may contain errors. If there were no errors, the 32 words added to this decoder's power would be the 32 words that would appear at the output of the error correction encoder.
Matches the word.

In the error correction decoder, the encoder performs interleaving processing and corresponding dinterleaving processing,
Error correction is performed after restoring the data order.

First, a dinterleaver (16) in which a 1-word delay circuit is inserted is provided for the odd-numbered transmission channel, and an inverter (16) is provided for the check word series.
7) (18) (19) (20) are inserted and supplied to the first stage decoder (21). In the decoder (21),
As shown in FIG. 4, the syndrome S1° is obtained from the parity check matrix Hcl and the input 327-code (v7).

S-th SIL S's are generated, and error correction is performed based on them. α is an element of G F (2') of (F(X)=x''+x'x'+x2-i-1).

From the decoder (21), 24 PCM data sequences and 4
checkword series appears, and 1 of this data series appears.
At least a 1-bit pointer (“l” if an error is included, “O” if not) indicating the presence or absence of an error is added to each word. This Figure 4 and Figure 5 below
In the figures and in the following description, one received word Wz is expressed as a unit Wz.

The output data series of this post-encoder (21) is supplied to a dinterleaver (22). The dinterleaver (22) is for canceling the delay processing performed by the interleaver (9) in the error correction encoder.
From the th transmission channel to the 27th transmission channel (27D, 26D, 25D...2D,
Delay circuits with different delay amounts are inserted. Dinter leaver (22) (1) Output is supplied to the next stage decoder (23). In the decoder (23), as shown in FIG. 5, a syndrome S2° is generated from the parity check matrix Hc2 and the 28 manually-written words.

S 2 Is S 22+ S 23 is generated,
Error correction is performed based on this.

The data sequence appearing at the output of the next-stage decoder (23) is supplied to an even-odd interleaver (24).

The even-odd dinter leaver (24) returns the PCM data series consisting of even-numbered words and the PCM data series consisting of odd-numbered words so that they are located on different transmission channels, and also returns the PCM data series consisting of odd-numbered words to different transmission channels. A one-word delay circuit is inserted for the PCM data series. At the output of this even-odd interleaver (24) there is a
A data series will be obtained. Although not shown in FIG. 3, a correction circuit is provided next to the even-odd dinterleaver (24) to make errors that could not be completely corrected by the decoder (21) (23) less noticeable. Corrections, such as average value interpolation, are performed.

In an example of the present invention, in the first stage decoder (21), 1
I even try to correct word errors.

If it is detected that there is an error of 2 or more words in one error correction block, an error is detected for all words in this error correction block except for 32 words or check words <28 words. At least a 1-bit pointer is added to indicate that there is a 1-bit pointer. For example, this pointer is set to "1" when there is an error, and "0" otherwise. Note that a pointer indicating that an error exists may be added even when the above-mentioned predetermined number of words is corrected during first-stage decoding.

When one word consists of 8 bits, a pointer is added as one bit higher than the most significant bit, and one word consists of 9 bits.
The data is converted into bits, processed by a dinterleaver (22), and supplied to the next stage decoder (23).

The next stage decoder (23) performs error correction using the number of error words or error locations in the first error correction block indicated by this pointer. FIG. 6 shows an example of error correction in the next-stage decoder (23). In FIG. 6 and the following explanation, the number of error words by the pointer is represented by Np, and the error location by the pointer is represented by Ei. It is expressed as Further, in FIG. 6, Y represents affirmation and N represents negation.

(1) Syndrome S2゜~S23 to check if there is an error
key 6ru o (Szo=S2+=S22=S2
3=0), it is assumed that there is no error. In that case, (N
Check whether p≦2+). If (Np≦2+), it is determined that there is no error, and the pointer in the error correction block is cleared (“0”).

If (Np>z+), consider that the syndrome detection is incorrect and leave the pointer as is, or
Set the pointers of all words in the block to "1'". Let zl be quite large, for example 14.

(2) If there is an error, check whether it is a one-word error by calculating the syndrome. In case of l word error, find the error location i. It is detected whether the error location i determined by this syndrome calculation matches the location determined by the pointer.

If there are multiple error locations by pointers, it is checked to see if it matches any of them.

(If i=Ei>, then it is checked whether (Np≦22). z2 is, for example, 1o. (N p≦22)
), this is determined to be a 1-word error, and the 1-word error is corrected. If (Np>22), it is dangerous to judge that it is a one-word error, so either the pointers are left as they are, or all words are regarded as errors and each pointer is set to "1".

In the case of (i4Ei), it is checked whether (N p≦23). 2. is a fairly small number, for example 3.

When (Np≦Za) holds, the one-word error at error location i is corrected by syndrome calculation.

In the case of (Np>z3), it is further checked whether (Np≦24). In other words, when (z3<Np≦24), it means that Np is too small even though the judgment of a one-word error due to the syndrome is incorrect, so the pointers of all words in that block are set to "l". do. Conversely, if (Np>z,), the pointer is left as is.

2. is, for example, 5.

(3) In the case where there is no single word error, (Np≦zi
), and if (Np≦ZS), the reliability of the pointer is poor, so the pointers of all words are set to "1". When (Np>z,), the pointer is left as is.

(4) As shown by the broken line in FIG. 6, it is also possible to correct up to M words using the error location using a pointer. For example, it is possible to correct up to 4 word errors. In this case, the error is corrected based on the error location indicated by the pointer. (N
p'F M ), either leave the pointers as they are or change the pointers of all words to indicate an error.

Note that the number of pointers indicating errors in one block is Np.
The specific numerical values of the comparison values 21 to zs are merely examples. The error correction code in the above example is 5
If there is a one-word error or more, there is a risk that it will be judged as no error, and if there is a four-word error or more, there is a risk that it will be judged as a one-word error. The comparison value can be set to an appropriate value by taking into account the probability of occurrence.

In the error correction decoder shown in FIG. 3, the first check word QI2111 Q+2h+++ Q+2a*
2* Error correction using Q1211+3 and second check word P1□,.

P1□yl+lI P 12R*2+ P 12R93
and error correction using . If each error correction is performed at least twice (actually, about twice), the error reduction resulting from the correction can be utilized to further increase the error correction ability. can. In this way, when a decoder is provided at a later stage, it is necessary to also correct the check word in the decoder (21) (23).

In addition, in the above example, the delay amount is varied by D as the delay processing in the interleaver (9), but unlike this regular change in the delay amount, it may be irregular. . Also, the second check word P1
is an error correction code that includes not only PCM data but also the first check word Q. Similarly, it is also possible to make the first check word QI include the second check word P1. Specifically, the second check word P is returned to the first check word P1. It can be fed to an encoder that forms words.

Note that even when a one-word error is corrected in the first-stage decoder (21), the pointers of all words in the error correction block containing this corrected one word are set to "1".
”, it is possible to further prevent detection errors and incorrect corrections.

〔Effect of the invention〕

As described above, according to the present invention, the first-stage decoder corrects errors up to a predetermined number that does not reach the given number of error-correctable words (four words in this example),
When it is detected that the number of errors exceeds the predetermined number, a pointer indicating the error is set for all words of the target error correction block, and the next encoder uses the error calculated from the error syndrome. The reliability of the location is checked by the number of pointers mentioned above, and when the number of pointers is within a predetermined value, the error indicated by the error location is corrected, so the number of error words exceeds the error correction capability. It is possible to prevent errors from being overlooked or incorrectly corrected by erroneously detecting that no errors exist, or by misunderstanding the number of errors that exist.
The reliability of decrypted data can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example of an error correction encoder to which the present invention is applied, FIG. 2 is a block diagram showing an arrangement during transmission, and FIG. 3 is a block diagram of an example of an error correction decoder. Fourth
5 and 6 are diagrams used to explain the operation of the decoder of the error correction decoder.

(1) (9) (11) is an interleaver, (8) (
10) is an encoder, (16) (22) (24> is a dinterleaver, and (21) (23) is a decoder.

Claims (1)

[Claims] The first check word generated from the first data series for error correction is different from the first data series, and the first check word is different from the first data series. A second check word generated from a second data series including the constituent words is received, and the transmitted data is checked for errors in the received data using the first and second check words. In an error correction method that performs correction,
In the first stage decoding in which errors are corrected in the second data series using the second check word,
In addition to correcting errors up to a predetermined number that does not reach the maximum correctable error number determined corresponding to the second check word, when it is detected that errors exist in excess of the predetermined number, the second check word In the subsequent decoding, a pointer indicating an error is set for all words of the error correction target block in the data series, and the error in the first data series is corrected using the first check word. The error location is determined from the syndrome generated using the first check word, and the number of pointers set during the previous stage decoding is checked, and if the number of pointers is within the predetermined value set, the error location is An error correction method designed to correct errors indicated by.