JPS63156355A - Optoelectronic integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to perform a very high speed operation of an optoelectronic integrated circuit (OEIC), by arranging a chip, on which photoelectrons are formed, and a chip, on which electronic elements are formed, on the same substrate, providing chip connecting electrodes, which are extened to the side surface of each chip, butting the electrodes, aud electrically connecting the electrodes. CONSTITUTION:A recess part is formed in a light receiving region of a semi-insulating InP (Si-InP) substrate 11 in a PIN photodiode chip. A p<+>-AlInAs layer 12, an n<->-InGaAs layer 13 and an n<+>-InGaAs layer 14 are sequentially formed so that the end surfaces of the layers are exposed in the recess part. The end surface of the p<+>-AlInAs layer 12 is connected to a p-type electrode (Au/Zn/Au) 16 through an opening part formed in an insulating layer (SiN) layer 15. The n<+>-InGaAs layer 14 is connected to an n-type electrode (Au/AuGe) 17. The electrodes 16 and 17 are extended to the end surface of the chip through extended electrodes (AuSn) 18 and 19. In an FET circuit chip, source and drain electrodes 25 and a gate electrode 24 are formed on an n-type region 22 on a substrate 21. The electrode, which is connected to the PIN diode, is extened to the end surface of the chip through an extended electrode 25. Since the chips can be connected in the shortest distance, the very high speed operation can be carried out.

Description

[Detailed Description of the Invention] [Summary] In an optoelectronic integrated circuit (OEIC) incorporating an optical element chip and an electronic element chip, a chip connecting electrode is formed extending to the side of the chip, and a side electrode of each chip is formed. By arranging the chips in close contact with each other on the substrate, inter-chip connections are made, creating an ultra-high-speed, highly integrated structure that reduces stray inductance and capacitance.

[Industrial application field]

The present invention relates to an ultra-high speed, highly integrated 0EIC using hybrid integration technology.

0B that incorporates optical elements and electronic elements into a small package
ICs are promising as future optical communication devices, ultra-high speed, ultra-highly integrated computer devices, and research and development are being actively conducted in various places.

[Conventional technology]

There are two main ways to connect optical and electronic devices: one is to monolithically integrate optical and electronic devices (including three-dimensional ICs), and the other is to fabricate them through separate semiconductor processes. Optical devices and electronic devices (VLSI)
This is a method of hybrid integration of

Hybrid integration technology has the advantage of being able to produce both optical devices and electronic devices at high yields.

This technology can be broadly classified into wire bonding method and flip-chip method, and the latter is superior in that it can extremely shorten the wiring length and can operate at high speed.

However, the conventional flip-chip method requires stacking two layers of chips, such as placing an optical device on top of an electronic device, and still has drawbacks in terms of chip alignment, heat dissipation, and device reliability. It is enough.

[Problem that the invention seeks to solve]

As described above, with the conventional hybrid structure, a highly reliable 0BIC capable of ultra-high-speed operation could not be obtained.

[Means for solving problems]

The solution to the above problem is to arrange a chip on which an optical element is formed and a chip on which an electronic element is formed on the same substrate, and each chip has a chip connection electrode formed extending to its side surface. , and an opto-electronic integrated circuit in which the electrodes are butted and electrically connected to each other.

[Effect]

According to the present invention, connections are made by bringing the electrodes on the sides of the chips into contact with each other, so there is no floating inductance or capacitance caused by wire wiring as in the wire bonding method, and the connections between chips can be made over the shortest distance, making ultra-high-speed operation possible. In addition, unlike the flip-chip method, chips are not stacked on top of each other, but instead all chips are placed with their surfaces facing upward, making the manufacturing process easier and reducing the risk of reducing device reliability.

〔Example〕

Figures 1 (1) and (2) illustrate one embodiment of the present invention.
FIG. 2 is a cross-sectional view and a partial perspective view of the EIC.

The figure shows a hybrid 0EIG in which a PIN photodiode as a light receiving element and an FET circuit as an electronic element are incorporated on a substrate.

The chip of the PIN photodiode is made of semi-insulating InP (
SI-1nP) p''-AIInAs ji1 so that the end face of each layer appears in the recess formed in the light receiving area of the substrate 11.
2. An n--InGaAs layer 13 and an n''-InGaAs layer 14 are formed in this order.

Insulating layer (SiN) deposited on the planarized chip surface
p”-AllnAs through the opening formed in layer 15
The end surface of the layer 12 is a p-type electrode (Au/Zn/Au) 16, and the n"JnGaAs layer 14 is an n-type electrode (Au/AuGe).
) connected to 17.

Each electrode 16.17 is an extension electrode (AuSn).
18 and 19 extend to the end face of the chip as shown in the perspective view.

The FET circuit chip has source and drain electrodes (Au
/AuGe) 23 and a gate electrode (WSi) 24 are formed.

The electrode connected to the PIN photodiode is an extension electrode (
AuSn) 25 or the like to the end surface of the chip.

The 0EIC is formed by arranging the above-mentioned PIN photodiode chip and PE7 circuit chip on an insulating substrate 1 so that their respective extension electrodes are butted against each other.

FIG. 2 is a perspective view of a semiconductor laser chip illustrating another embodiment of the present invention.

The figure shows a semiconductor laser chip as a light emitting element when a light emitting element is used instead of a light receiving element in the hybrid 0BIC of FIG. 1.

The semiconductor laser chip is made of p''-GaAs so that the end surfaces of each layer are exposed in the recesses formed in the 5l-GaAs substrate 31.
Buffer layer 32, p-AlGaAs cladding layer 33, multilayer quantum well structure (MQW) light emitting layer 34, n-AlGaA
An s-cladding layer 35 and an n''-GaAs cap N36 are formed in this order.

37 and 38 form a Znn diffusion state region, a disordered region that confines light in the lateral direction.

An n''-GaAs cap layer 36 is applied through an opening formed in an insulating layer 39 deposited on the planarized chip surface.
is a p-type electrode (Au/AuGe) 40, p''-GaA
The end surface of the s-basso layer 32 is an n-type electrode (Au/Zn/Au
) Connected to 41.

Each electrode 40.41 is an extension electrode (AuSn) 4
2.43 extends to the chip end face as shown in the figure,
It can be connected to the FET circuit.

〔Effect of the invention〕

As described above in detail, the hybrid structure according to the present invention provides a highly reliable 0EIC capable of ultra-high-speed operation.

[Brief explanation of the drawing]

Figures 1 (1) and (2) illustrate one embodiment of the present invention.
A cross-sectional view and a partial perspective view of an EIC, and FIG. 2 is a perspective view of a semiconductor laser chip illustrating another embodiment of the present invention. In the figure, 1 is a substrate, 11 is a 5I-InP substrate, 12 is a p''-AllnAs layer, 13 is an n-InGaAs layer, 14 is an n''-InGaAs layer, 15 is an 8i layer and is a SiN layer, 16 is an n-type Electrodes (Au/Zn/Au), 17 is an n-type electrode (Au/AuGe), 18.19 is an extension electrode (AuSn), 21 is a 5l-GaAs substrate, 22 is a source, drain, and channel region; 23 are source and drain electrodes (Au/AuGe), 24
is gate-oriented (Xiong 5i) 2. 25 is an extension electrode (8uSn), 31 is a 5r-GaAs group, 32 is a p''-GaAs haphazard layer, 33 is a p-AlGaAs cladding layer, 34 is an MQW light emitting layer, 35 is an n-AlGaAs cladding layer, 36 is an n''-GaAs cap layer, 37.38 is a Zn diffusion region and disordered region, 39 is an insulating layer, 40 is an n-type electrode (Au/AuGe), 41 is an n-type electrode (Au/Zn/Au), 42 .43 Extension electrode (AuSn) Fuki 1 Figure 2 (2)

Claims (1)

[Claims] A chip formed with an optical element and a chip formed with an electronic element are arranged on the same substrate, each chip having a chip connection electrode extending to its side surface, An optical/electronic integrated circuit characterized in that the electrodes are butted against each other and electrically connected to each other.