JPS63156348A - Semiconductor device - Google Patents

Abstract

PURPOSE:To implement high density and high integration, by providing connecting electrodes and internal wirings, which connect the electrodes electrically, on the upper and rear surfaces of semiconductor device chips, coupling said connecting electrodes of the facing semiconductor device chips, and providing a constitution of three-dimensional laminated layers CONSTITUTION:All surfaces 16-1-16-4 of semiconductor device chips 11-1-11-4 face upward the facing bumps are bonded by a thermocompressing bonding method, electrically connected and mechanically coupled. Semiconductor device parts 13-1-13-4 on the semiconductor device chips 11-1-11-4 are electrically connected to the terminals on a ceramic substrate 12 through the bumps and internal wirings. 4 semiconductor device 10 has a structure, wherein the semiconductor device chips 11-1-11-4 are electrically connected themselves and laminated in three-dimensional four layers. Thus the high density and high integration of the semiconductor device parts can be implemented.

Description

[Detailed Description of the Invention] [Summary] The semiconductor device of the present invention provides a semiconductor device chip itself with an electrically inscribed PAR function, stacks three or more layers of semiconductor device chips themselves, and achieves a high density semiconductor device. This is aimed at high integration.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a semiconductor device formed by stacking semiconductor device chips.

[Conventional technology]

The structure of a conventional semiconductor device of this type is shown in FIG. In the figure, reference numerals 1 and 1a each represent a semiconductor device chip. A semiconductor device chip 1 has a semiconductor device portion 2 on its surface.
It is an M4 structure consisting of a substrate 3 having a 300 mm diameter, wiring portions 4 and 5 on the surface of the substrate, a polyimide layer 6 covering the wiring portion 4.5, and an AU bump 7°8 at the tip of the wiring portion 4.5. Another semiconductor device chip 1a has a similar configuration to the above-described semiconductor device chip 1, and corresponding parts are designated by the same reference numerals with a suffix a.

Semiconductor device chips 1 and 1a each have a surface 9.9
With their a sides facing each other, Au bumps 7 and 7a and 8 and 8a are bonded and electrically and mechanically connected and integrated, resulting in twice as high integration as before. It is planned.

[Problem that the invention seeks to solve]

However, in the semiconductor device with the above configuration, the V4 layer of the semiconductor device chip is limited to two layers, and it is impossible to stack three or more layers, so it is impossible to achieve higher integration than shown in FIG. The problem was that there was no.

[Means for solving problems]

The semiconductor device of the present invention has a structure in which a semiconductor F device chip is provided with connection electrodes on its front surface and an internal wiring that electrically connects the connection electrodes on the front and back sides, and the semiconductor The device chip has a configuration in which the facing connection electrodes are bonded and stacked three-dimensionally.

[Operation] Since the semiconductor device chip itself has electrical connection means on both its front and back surfaces, three or more layers of semiconductor device chips can be stacked without using special members for connection.

(Embodiment) FIG. 1 shows a semiconductor device 10 according to a first embodiment of the present invention. In the figure, 11-1 to 11-4 are semiconductor device chips, respectively, which are stacked on a ceramic substrate 12.

As shown in FIG. 2, the semiconductor device chip 11-1 includes a semiconductor substrate 14-1 on which a semiconductor device portion 13 is formed.

15-n and 15-12 are A as connection electrodes, respectively.
It is a bump of utJ, and is formed on the surface 16-+, which is the same surface on which the semiconductor device portion 13-1 is formed. semiconductor device section 13-1 and bump 15-n,
Wiring is provided between 15 and 12.

17-n and 17-12 are Aug as connection electrodes, respectively.
J! It is a bump of J and is formed on the back surface 18-1.

A through hole 19-n is provided in the semiconductor substrate 14-n.

19-12 is drilled inside, and internal wiring 20-
n, 20-12 are formed. Bump 15-
11 and 17-I+ are electrically connected by internal wiring IQ 20-n. Bumps 15-12 and 17-12
is connected to by internal wiring 20-12 and surface wiring 21-1. Note that the bump 15-n.

15-12, 17-n, and 17-12 are arranged at positions t where connections are required, respectively.

22-1 is an insulating layer formed on the front surface of the semiconductor substrate 14-1 and the inner surfaces of the through holes 19-n and 19-12.

Other semiconductor device chips 11-2.11-3.11
-s has the same configuration as the above semiconductor chip 11-1, and the corresponding parts are attached. 2゜3.4, 21.22
．． The same reference numerals as 31.32 and 41.42 are used, and the explanation thereof will be omitted.

As shown in FIG. 1, the semiconductor device chips 11-1 to 11-4 are all oriented with the surfaces 16-I to 16-4 facing upward, and the opposing bumps are bonded by thermocompression bonding. , electrically connected and mechanically coupled. Each semiconductor device chip 11-1~
The semiconductor device portions 13-11-4 to 13-4 are electrically connected to terminals (not shown) on the ceramic substrate 12 through bumps and internal wiring.

The semiconductor device 10 includes semiconductor device chips 11-1 to 11-1.
11-4 are three-dimensionally stacked in four layers while being electrically connected to each other, and high density and high integration of the semiconductor device section is achieved.

Note that the semiconductor device chips 11-1 to 11-4 are
For example, the semiconductor device 1o is stacked without using other jigs such as printed circuit boards, and the semiconductor device 1o is configured with a minimum number of parts.

In addition, only semiconductor device chips 11-1 to 11-↓ that have been previously inspected and found to be non-defective are used, and the percentage of non-defective semiconductor devices 10 is high.

Further, the respective semiconductor device chips 11-1 to 11-4 are stacked with the surfaces 16-1 to 16-4 facing upward. For this reason, each semiconductor device chip 1
The state of the semiconductor device portions 1-1 to 11-4 after lamination can be visually checked, which is convenient.

Furthermore, the number of stacked semiconductor device chips is not limited to four, but can be set arbitrarily.

Further, the bumps 15-n, 17-n, etc. may be made of solder, and in this case, solder flow can be used, and the pressure at the time of chip bonding can be alleviated.

3 and 4 respectively show the second embodiment of the present invention. A semiconductor device 30.40 according to a third embodiment is shown. In each figure, parts that substantially correspond to those shown in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

The semiconductor device 30 in FIG. 3 has a structure in which an upwardly facing semiconductor device chip and a downwardly facing semiconductor device chip are mixed. Semiconductor device chips 11-1 to 11-
4 is the chip 11-1 of the first layer and the depth 1 of the fourth layer.
1-4 faces upward, and the second layer depth 11-2 and third layer chip 11-3 face downward and are electrically connected to each other.

The semiconductor device 40 shown in FIG. 4 has a structure in which upward-facing chips and downward-facing chips are alternately arranged. This semiconductor device 4
0 is, for example, a bonded body 41 in which a first layer chip 11-1 and a second layer depth 11-2 are joined by abutting their surfaces against each other, and a chip 11-1 in a third layer [1]. 3
and the fourth layer chip 11-4 are combined together.
Each bonded body 41, 42 was made separately and tested, and the bonded bodies 41, 42 that were good were bonded with their back surfaces butted against each other to form a four-layer structure.

[Efficacy of invention Song Dynasty]

According to the present invention, three or more layers of semiconductor device chips can be stacked three-dimensionally in either direction, without requiring special parts for connection, and without distinguishing between front and back surfaces.
High density and high integration of semiconductor device chips can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional front view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device chip shown in FIG. FIG. 4 is a vertical sectional front view of a semiconductor device according to a third embodiment of the present invention, and FIG. 5 is a sectional view of an example of a conventional semiconductor device. In the figure, 10, 30, and 40 are semiconductor devices, 11-1 to 11-4 are semiconductor device chips, 12 is a ceramic bulb, 13=1 to 13-4 are semiconductor device parts, and 14-1 to 14-4 are semiconductor device parts.
1/l-s is a semiconductor substrate, 15-n to 15-42.17-+1 to 17-42 are bumps, 16-1 to 16-4 are front surfaces, 18-1 to 18-4 are back surfaces, 19-n , 1912 are through holes, 21-n to 21-42 are internal wirings, 21 is surface wiring, 22-1 to 22-4 are insulating layers, and 41.42 is a bonded body. Agent poor burial ten well figure low -'-'”':”t.'; Kiichi. four! Hokoji water rate] 5 Plr, Houki l Yuuseyu 11 Haru size 1 Mizutama Tomai Kugisho 1 Figure i Figure % - Noya 1 bottle 〒 Space Δ Space now - y7? ) Q [City 19
Hanaken 42 Mibushi PI l: Yoru Hantone Ohonzul's Hatake Mimesu Sho 3 Broom Illustration 3 Illustrations

Claims (1)

[Claims] Semiconductor device chip (11-_1 to 11-_4)
, its front side (16-_1 to 16-_4) and back side (1
Connecting electrodes (15-_1_1) to 8-_1 to 18-_4)
~15-_4_2, 17-_1_1~17-_4_2)
and internal wiring (21-_1_1 to 21-_4_2) for electrically connecting the above-mentioned front and back connection electrodes.
The semiconductor device chip (11-_1 to 11-_4)
The above connection electrodes (15-_1_1 to 15-
_4_2, 17-_1_1 to 17-_4_2) A semiconductor device having a three-dimensionally stacked structure in which comrades are bonded together.