JPS63155771A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase output resistance, by depositing a metal in a source formation region so as to form a metallic film on side walls in a recessed region before side wall films on a first insulating film are utilized to form a gate electrode. CONSTITUTION:A silicon film is made to grow as an insulating film 3 so as to form a recessed region 4 on a semi-insulating buffer layer 1 and an active layer 2 which are piled on a surface of a substrate. Part of the surface of the active layer 2 is shaved off to form a recessed region 5. Successively, metal evaporation is performed inclinedly from a drain side to a source side so as to form a metallic film 6, and then a SiO2 film 8 is made to regrow. Since a growth rate on the metal is small in this case, the SiO2 film 8 on the surface of the metallic film 6 becomes small in thickness. Next, the regrowing insulating film 8 and the Ti metallic film 6 are shaved off. Since thickness of a side wall film 9S an a source side is smaller than that of a side wall surface 9D on a drain side in this case, and length lD of the recessed region on the drain side is relatively larger than that lS of the recessed region on the source side, so that drain resistance can be relatively increased.

Description

Detailed Description of the Invention [Summary] A method for manufacturing a semiconductor device including a step of forming a gate electrode using a sidewall film regrown on the sidewall of a recessed region, the method comprising: forming a gate electrode using a sidewall film regrown on the sidewall of a recessed region; As a treatment, a metal that reduces the regrowth rate of the film is deposited obliquely from the drain side to the source side, thereby increasing the output resistance and making it possible to increase the gain of the FET.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for forming a gate electrode of a field effect transistor.

Due to their characteristics, FETs are used in a wide range of applications, including amplifiers that require high input impedance, and even high frequencies.The gate electrode used to control the degree of amplification has been miniaturized to amplify high-frequency signals. There is a tendency to Therefore, a method is required for forming fine D1-electrodes while maintaining high output resistance.

[Conventional technology]

Conventionally, one method for forming a fine gate electrode at the Submicron level is to utilize a regrown film formed on the sidewall of a recessed region for forming the gate electrode.

FIGS. 2(a) to 2(f) show a conventional process for forming a fine gate electrode using the regrown film (referred to as quantum sidewall film) on the sidewall. First, an insulating film 23 is formed on the semi-insulating buffer layer 21 and the active layer 22 on the surface of the semiconductor substrate.
(step (a)), patterning for the gate I/electrode is performed, and a part of the insulating film 23 is made 1" using resist.
Lie etching is performed to form a one-noise region 24 (step (b)). Furthermore, the insulating film 25 is grown again (step (C)). After that, anisotropic dry etching is performed on the entire surface to scrape off the regrown insulating film 25, and the sidewall film F1 is removed.
and F2 remain (step (d)), step (e) to form a fine gate electrode 26 using these sidewall films F1 and F2, and finally unnecessary insulating film 23 and sidewall films FI and F2. I try to scrape it off.

Note that a dashed dotted line 0 shown in step (b) indicates a recess region 2 formed in the insulating film 23 for forming a gate electrode.
4 and corresponds to an intermediate position for both the source and drain electrodes (not shown).

[Problem that the invention seeks to solve]

”According to two consecutive conventional processes, sidewall membranes F and F
2 are formed with the same thickness β, the center line GC1 of the gate electrode 26, that is, the center line of the channel region in the active layer 22 controlled by the control voltage applied to the gate electrode, is the same as that in step (f). As shown, it coincides with the center line 0 between the source electrode and the drain electrode described above.

In other words, the gate electrode is arranged such that the source electrode and the drain electrode have a symmetrical positional relationship with respect to the gate electrode.

Therefore, when actually used as F F, T, the source side resistance and the drain side resistance are both the same value, and when one is considered as a reference, the source side resistance (input resistance)
There is a problem that the resistance becomes relatively large, and conversely there is a problem that the drain side resistance (output resistance) becomes relatively small. This also affects the low FET gain of the FET, and moreover becomes more noticeable as the gate electrode becomes finer.

The present invention has been made in view of the problems in the prior art described in (b), and provides a semiconductor device that can relatively increase the output resistance and increase the gain even when the gate electrode of the FET is miniaturized. The purpose is to provide a manufacturing method.

[Means and operations for solving the problem] A method for manufacturing a semiconductor device according to the present invention includes removing a part of the first insulating film grown on -1- of the semiconductor layer to form a recess region. a first step, and a second step of regrowing a second insulating film in the recessed region and forming a gate electrode using the sidewall film on the first insulating film thus formed. Between the first step and the second step, a metal that reduces the growth rate of the second insulating film is deposited in an oblique direction from the top of the drain formation region toward the source formation region. The present invention is characterized by comprising a third step of forming a metal film on the side wall of the source formation region in the recess region.

〔Example〕

FIGS. 1(a) to (i) show F as an embodiment of the present invention.
Steps are shown to illustrate Day 1-electrode formation in ET.

First, in step (a), an insulating It! 3 is a silicon oxide (SiO□) film or a silicon nitride (Si3N4) film.
) to grow a film. In step (b), patterning for the gate electrode is performed, and a part of the insulating film 3 is dry etched using a resist to form a recess region 4. The center line of this recessed region is indicated by a dashed line O and corresponds to a position midway between the source electrode and the drain electrode (not shown). Further, in step (c), a part of the surface of the active layer 2 corresponding to the recessed region 4 is etched away by wet etching to form a recessed region 5. In this recess region 5, the cross-sectional area of the channel serving as a current path from the source electrode to the drain electrode is reduced, so that the current can be sufficiently pinched off. Therefore, this recessed area 5 serves to improve the controllability of the cage.

In the next step (d), metal (titanium (Ti) in this example) is vapor-deposited in the direction indicated by the arrow, that is, diagonally from the drain side to the source side, to a thickness of 100 ~
300 metal films 6 are formed. As a result, the metal film 6 is formed on the upper surface of the insulating film 3 and on the side wall 7 on the source side, as shown in the figure. A side wall 7 formed on the drain side. not formed on top.

In the next step (e), the SiO□ film 8 as an insulating film is
°ζ is regrown using the D (chemical vapor deposition) method. In this case, since the growth rate of the SiO□ film is generally low on metal, the S
The iO□ film 8 grows thin < (1000 to 2000 people), and otherwise grows thick < (3000 people). Process (f)
Then, the regrown insulating film 8 and the Ti metal film 6 are scraped off by anisotropic dry etching using CF4 (carbon tetrafluoride) gas to obtain dimensions for a fine gate electrode. In this case, the thickness of the sidewall film 9s on the source side including the metal film is equal to the thickness of the sidewall film 9s on the drain side. When the gate electrode 10 is formed in a subsequent process, the center line GC of the gate electrode is biased toward the source side from the position 0 between the source electrode and the drain electrode described above.

Steps (g) to (i) show the process of forming a gate electrode. First, in step (g), titanium, platinum, gold (T
i /PL /Au) is deposited over the entire surface, and in the next step (h), after buttering, unnecessary parts are removed by milling, and in the last step (i), unnecessary insulating film is removed by wet etching. 3
, the side wall films 9S, 9D, and the metal film 6 on the side wall 7s are scraped off. In the diagram! ! 3 and l. are respectively on the source side,
Indicates the length of the recess region on the drain side.

According to the manufacturing process shown in FIG. 1, the SiO□ film 8 is regrown and the sidewall film 9. and 9. Prior to the process of forming the gate electrode 10 (steps (e) and (f)), the center of the gate electrode 10 is The line GC can be displaced from position 0 between the source electrode and the drain electrode to the source side.

This determines the length of the recess area on the drain side! , is relatively long compared to the length l of the recess region on the source side. In other words, on the drain side, the recess region is long in the direction of current flow, so the drain resistance (output resistance) can be relatively increased compared to a conventional FET with a symmetrical configuration. It is possible to increase the gain as a FET.

In the embodiment shown in FIG. 1, Ti is used as the metal to be vapor deposited, but the metal is not limited to this, and for example, Au may be used.

However, in this case, even if dry etching is performed using CF4 gas in step (f), it is difficult to scrape off the A and U films cleanly, so it is necessary to further scrape them off by milling.

〔Effect of the invention〕

As explained above, according to the present invention, even when the gate electrode of an FET is miniaturized, the output resistance is increased by making the gate recess region on the drain side relatively longer than the gate recess region on the source side. Gain can be increased.

[Brief explanation of the drawing]

FIGS. 1(a) to (i) show an FE as an embodiment of the present invention.
FIGS. 2(a) to 2(f) are process diagrams for explaining gate electrode formation in an FET as an example of a conventional type. (Explanation of symbols) 1... Semi-insulating buffer layer, 2... Active layer, 3... Insulating layer, 4.5
... Recessed region, 6... Metal layer, 1s, 1o...
- Side wall, 8...SiO□ film, 9, . 9D... Side wall film, 10... Gate electrode.

Claims (1)

[Claims] 1. A first step of removing a part of the first insulating film grown on the semiconductor layer to form a recessed region, and re-forming a second insulating film in the recessed region. and a second step of forming a gate electrode using a sidewall film on the first insulating film formed by the first insulating film. During the process, a second insulating film (8
) is deposited obliquely from the top of the drain formation region toward the source formation region, and a metal film ( 6) A method for manufacturing a semiconductor device, comprising a third step of forming. 2. between the first step and the third step, further comprising a step of forming a second recess region (5) on the surface of the semiconductor layer (2) within the recess region (4); A method for manufacturing a semiconductor device according to claim 1.