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JPS6315431A - Molding die for manufacturing semiconductor device - Google Patents

Molding die for manufacturing semiconductor device

Info

Publication number
JPS6315431A
JPS6315431A JP16025586A JP16025586A JPS6315431A JP S6315431 A JPS6315431 A JP S6315431A JP 16025586 A JP16025586 A JP 16025586A JP 16025586 A JP16025586 A JP 16025586A JP S6315431 A JPS6315431 A JP S6315431A
Authority
JP
Japan
Prior art keywords
mold
abutting surface
molds
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16025586A
Other languages
Japanese (ja)
Inventor
Michio Ishihara
石原 通男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16025586A priority Critical patent/JPS6315431A/en
Publication of JPS6315431A publication Critical patent/JPS6315431A/en
Pending legal-status Critical Current

Links

Landscapes

  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: To eliminate the need for die matching by forming a recessed section to an abutting surface in one mold in a pair of molds and substantially shaping the abutting surface of the other mold in a plane. CONSTITUTION:Recessed sections 11b, 11c are formed to the abutting surface 11a of a top force 11, no recessed section is shaped to the abutting surface 12a of a bottom force 12, and the abutting surface 12a is formed substantially in a plane 12b. A tablet is charged into a charging port 17, and pushed by a plunger, thus filling the insides of cavities 13, 14 with a resin through a runner and a gate, then sealing semiconductor chips 15 with the resin together with one parts of lead frames 16. The molds 11, 12 are separated, molded forms are removed from a molding die 10, and the lead frames are cut, thus acquiring a semiconductor device 19 having structure in which leads 16a are bent in the direction of the height of a resin package 18 in the resin package 18 and one end sides 16a-1 are exposed to the lower surface of the resin package 18 as terminals and extended to both sides. Accordingly, the die-matching of the top force 11 and the bottom force 12 is unnecessitated substantially.

Description

【発明の詳細な説明】 〔概要〕 本発明は半導体装4製逍用モールド金型において、一対
の型のうち一方の型にのみ四部を形成し、他方の型は平
坦面とし、型合せが不要な構成とし、且つ該他方の型は
共用化し、上記一方の型だけを交換して、型番の異なる
半導体装置の成形に対応しうる構成としたものである。
[Detailed Description of the Invention] [Summary] The present invention provides a mold for manufacturing four semiconductor devices, in which the four parts are formed in only one of a pair of molds, the other mold has a flat surface, and the molds can be matched easily. This configuration is unnecessary, the other mold is shared, and only one of the molds can be replaced to accommodate molding of semiconductor devices of different model numbers.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置製造用モールド金型に関する。 The present invention relates to a mold for manufacturing semiconductor devices.

〔従来の技術〕[Conventional technology]

第8図は従来の半導体装置製造用モールド金型1の構造
を示す。図中、2は上型、3は下型であり、夫々の突き
合せ面2a、3aに凹部2b。
FIG. 8 shows the structure of a conventional molding die 1 for manufacturing semiconductor devices. In the figure, 2 is an upper mold, 3 is a lower mold, and recesses 2b are formed on the butting surfaces 2a and 3a, respectively.

2G、3b、3cが形成しである。上下の型2゜3は、
半導体チップ4が固着されたリードフレーム5を問に挟
んで、且つ凹部2bと3b、及び2Cと3Cとを相対向
させて組み合わされている。
2G, 3b, and 3c are formed. The upper and lower molds 2゜3 are
The recesses 2b and 3b and the recesses 2C and 3C are combined with the lead frame 5 to which the semiconductor chip 4 is fixed sandwiched therebetween.

四部2bと3bとがキ11ビティ6、凹部2Cと3Cと
がキ11ビティ7を形成する。
The four parts 2b and 3b form a hole 6, and the recesses 2C and 3C form a hole 7.

8はタブレット投入口、91,1各型2.3に埋め込ま
れたヒータである。
8 is a tablet inlet, 91, 1 is a heater embedded in each mold 2.3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

その内部に半導体チップ4をリードフレーム5の一部と
共に支持し、樹脂が充填される4−ヤビティ6.7は、
型2の凹部2b (2C)と型3の凹部3b(3c)と
が相対向して形成するものであり、以下に述べる問題点
があった。
The 4-cavity 6.7 supports the semiconductor chip 4 together with a part of the lead frame 5 inside and is filled with resin.
The recess 2b (2C) of the mold 2 and the recess 3b (3c) of the mold 3 are formed to face each other, and there is a problem described below.

まず、成形に際しての型合せの際には、凹部2b (2
c)と凹部3b(3c)とが正確に相対向するように、
型2.3を精度良く位置合せする必要があり、型合せ作
業が困難であるという問題点があった。
First, when matching the molds during molding, the recess 2b (2
c) and the recessed portion 3b (3c) accurately face each other,
There was a problem in that it was necessary to align the molds 2 and 3 with high precision, making the mold alignment work difficult.

また、半導体装置の型番毎に、専用の上型と下型とより
なるモールド金型を用意する必要があり、コストがかさ
むという問題点があった。
Furthermore, it is necessary to prepare a molding die consisting of a dedicated upper mold and a lower mold for each model number of the semiconductor device, resulting in an increase in cost.

また、型番の異なる半導体装置を製造するに際しては、
成形態に取り付けられている上型と下型との両方を交換
する必要があり、交換に時間がかかり、しかも上記のよ
うに困難な型合せ作業を必要とするという問題点があっ
た。
Also, when manufacturing semiconductor devices with different model numbers,
It is necessary to replace both the upper mold and the lower mold attached to the molding form, which is time consuming and requires difficult mold matching work as described above.

〔問題点を解決ηるための手段〕 本発明は、半導体チップをこれが固着されたリードフレ
ームと共に樹脂封止する一対の型よりなる半導体装置製
造用モールド金型において、該一対の型のうち、一方の
型のみにその突ぎ合せ面に四部を形成し、 他方の型は、その突き合せ面を実質上平坦面とした構成
である。
[Means for Solving the Problems] The present invention provides a molding die for manufacturing a semiconductor device consisting of a pair of dies for resin-sealing a semiconductor chip together with a lead frame to which the semiconductor chip is fixed. Only one mold has four parts formed on its abutting surface, and the other mold has a substantially flat abutting surface.

〔作用〕[Effect]

この構成は、型合せを不要とし、且つ上記他方の型につ
いては製造しようとする半導体装置の種類を迎えても共
通に使用可能とし、金型の設置及び取り苔えの作業性を
向上させ、しから上記一方の望についてだけ半導体装l
の種類に応じて用意づれば足り、金型コストの低減が図
られる。
This configuration eliminates the need for mold matching, and allows the other mold to be used in common regardless of the type of semiconductor device to be manufactured, improving the workability of mold installation and removal, However, only for one of the above requirements is the semiconductor device l
It is sufficient to prepare one according to the type of mold, and the mold cost can be reduced.

〔実施例〕〔Example〕

第1図は本発明の一実施例になる半導体装置製造用モー
ルド金型10を示す。図中、11は上型、12は下型で
ある。上型11の突き合せ面11aには凹部11b、1
1cが形成しである。下型12の突ぎ合せ面12aには
凹部は形成されておらず、突き合せ面12aは実質上平
坦面12bとなっている。
FIG. 1 shows a molding die 10 for manufacturing a semiconductor device, which is an embodiment of the present invention. In the figure, 11 is an upper mold, and 12 is a lower mold. The abutting surface 11a of the upper mold 11 has recesses 11b, 1
1c is formed. No recess is formed in the abutting surface 12a of the lower die 12, and the abutting surface 12a is a substantially flat surface 12b.

凹部11b(11c)がその開口を平坦面12bにより
塞がれてギャビテイ13.14を形成している。
The opening of the recessed portion 11b (11c) is closed by the flat surface 12b to form a gap 13.14.

型11.12の間には、第2図(A)、(B)。Between the molds 11 and 12, FIGS. 2(A) and (B).

(C)に示す、半導体チップ15が固着されてワイヤボ
ンディングされた立体形状のリードフレーム16が挟ま
れており、半導体チップ15及びリード16aがキャビ
ティ13.14内に支持されている。
A three-dimensional lead frame 16 to which a semiconductor chip 15 is fixed and wire-bonded is sandwiched, as shown in (C), and the semiconductor chip 15 and leads 16a are supported within the cavity 13.14.

タブレッ1− (図示せず)を投入口17内に投入して
プランジj+ (図示Uず)で押圧することにより、樹
脂がランチ及びゲート(共に図示せず)を通してキャビ
ティ13.14内に充填され、半導体チップ15がリー
ドフレーム16の一部と共に樹脂1・1止される。この
後、型11.12を離して成形品をモールド金型10よ
り取り外し、リードフレームを切断することにより、第
3図乃至第5図に示すように、リード16aが樹脂パッ
ケージ18内でこの高さ方向に屈曲しており、この一端
側16a−1が端子として樹脂パッケージ18の下面に
露出して且つ両側に延出した格上の半導体装置19が得
られる。
By putting the tablet 1- (not shown) into the inlet 17 and pressing it with the plunger j+ (U not shown), the resin is filled into the cavity 13.14 through the launch and gate (both not shown). , the semiconductor chip 15 and a part of the lead frame 16 are fixed in resin 1.1. Thereafter, the molds 11 and 12 are released, the molded product is removed from the mold die 10, and the lead frame is cut, so that the leads 16a are placed at this height within the resin package 18, as shown in FIGS. A superior semiconductor device 19 is obtained, which is bent in the horizontal direction, with one end side 16a-1 exposed as a terminal on the lower surface of the resin package 18 and extending to both sides.

第1図より分かるように、モールド金型10は、キャビ
ティ13.14が、上型11の凹部11b(11c)と
下型12の平坦面12bとにより形成される構成である
ため、キャごティを形成するための上型11と下型12
との型合せは実v1的に不要となり、型11.12の成
形橢への取(44)は容易に且つ作業性良く行ないうる
As can be seen from FIG. 1, the molding die 10 has a structure in which the cavities 13.14 are formed by the recessed portion 11b (11c) of the upper mold 11 and the flat surface 12b of the lower mold 12, so that the cavity 13. Upper mold 11 and lower mold 12 for forming
It is actually unnecessary to match the molds 11 and 12 to the molding shell (44) easily and with good workability.

また、下型12については凹部が形成されていないため
、これに凹部を形成した構成に比べて下型12自体の構
造が簡単となり且つ¥lJ造コフコスト価となる。これ
により、モールド金型10も、第8図の従来のモールド
金型1に比べて構造が簡単となって且つ安価となる。
Furthermore, since no recess is formed in the lower mold 12, the structure of the lower mold 12 itself is simpler than in a structure in which a recess is formed, and the cost is reduced to ¥1J. As a result, the molding die 10 also has a simpler structure and is less expensive than the conventional molding die 1 shown in FIG. 8.

次に、第3図の半導体装置19とは型番の異なる第7図
に示す形状の半導体装置20を製造しようとする場合の
、モールド金型10の変更について説明する。
Next, a description will be given of changes to the mold 10 when manufacturing a semiconductor device 20 having a shape shown in FIG. 7 and having a different model number from the semiconductor device 19 shown in FIG. 3.

この場合には、第6図に示す半導体装釘製造用モールド
金型21を使用する。このモールド金型20は、第1図
の下型12は変えずにそのまま使用し、上型11だけを
突き合せ面23aに第6図中の樹脂パッケージ22に対
応した形状の凹部23bを有する上型23に変更した構
造である。
In this case, a semiconductor nail manufacturing mold 21 shown in FIG. 6 is used. In this molding die 20, the lower mold 12 in FIG. 1 is used as is, and only the upper mold 11 has a recess 23b in a shape corresponding to the resin package 22 in FIG. 6 on the abutting surface 23a. This is a structure changed to type 23.

このときにも、上型23と下型12との型合せは不要で
ある。また下型12は取り外さずに固定したままであり
、上型11だけを交換すればよく、このことによっても
、モールド金型を取り苔える作業は容易に行なわれる。
Also at this time, there is no need to match the upper mold 23 and the lower mold 12. Furthermore, the lower mold 12 remains fixed without being removed, and only the upper mold 11 needs to be replaced, which also facilitates the work of removing the mold.

このモールド金型10を使用して、第6図に示す形状の
半導体装置20が製造される。
Using this mold 10, a semiconductor device 20 having the shape shown in FIG. 6 is manufactured.

なお、第1図及び第7図中、24は型内に埋め込まれた
ヒータである。
In addition, in FIG. 1 and FIG. 7, 24 is a heater embedded in the mold.

上記より分かるように本実施例のモールド金型によれば
、下型12が共用化されるため、製造しようとする半導
体装■の種類の数だけ、上型と下型とを対として用意す
る必要はなく、上記種類毎に上型だ【ノを用意すればよ
く、金型コストを低減しうる。
As can be seen from the above, according to the mold of this embodiment, the lower mold 12 is shared, so that pairs of upper molds and lower molds are prepared as many as the number of types of semiconductor devices to be manufactured. It is not necessary to prepare an upper mold for each of the above types, which can reduce mold costs.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、組み合わされてモールド金型を構成す
る一対の型のうち、一方にのみ凹部を形成し、他方は平
坦面とし、キャビティを実質上上記の凹部のみにより形
成する構成であるため、型ずれの心配がなく、型合せが
不要となり、成形はへの取り付けを容易に行なうことが
出来、しかも上記他方の型は共用化し、上記一方の型の
みを複数種類用意すれば足り、金型コストの低減を図る
ことが出来、しかも製造しようとする半導体装置の種類
に応じてモールド金型を取り替える作業を能率良く行な
うことが出来るという特長を有する。
According to the present invention, the recess is formed in only one of the pair of molds that are combined to form a mold die, and the other is a flat surface, so that the cavity is substantially formed only by the recess. , there is no need to worry about mold misalignment, there is no need to match the molds, the molding can be easily attached to the mold, and the other mold can be shared, it is sufficient to prepare multiple types of the one mold, and the metal The present invention has the advantage that mold costs can be reduced, and the work of replacing molds depending on the type of semiconductor device to be manufactured can be carried out efficiently.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体装置tJ造用モールド金型の一
実施例を示す図、 第2図(A)は第1図のモールド金型に挟み込まれる半
導体チップが固着されたリードフレームの平面図、 第2図(B)、(C)は夫々第2図(A)中IIB−I
IB線、I[C−1f(JJに沿う断面矢視図、第3図
は第1図のモールド金型により製造された半導体装置の
斜視図、 第4図及び第5図は夫々第3図中IV −IV線及び■
−v線に沿う断面矢視図、 第6図は、第1図中下型は共用し、上型だけを交換して
構成したモールド金型を示す図、第7図は第6図のモー
ルド金型により製造された半導体装置の斜視図、 第8図は従来の半導体装置製造用モールド金型を示す図
である。 図において、 10.21は半導体装置製造用上−ルド金型、11.2
3は上型、 11a、12a、23aは突き合せ面、11b、11c
、23bは凹部、 12は下型、 12bは平坦面、 13.14はキャビティ、 15は半導体チップ、 16はリードフレーム、 18.22は樹脂パッケージ、 19.20は半導体装置である。 10牢番岑ト1製編用 一4=−1し)づ=ピ覧L 19牛稼惨妓量 CB) )、−11C (C)          (A) 峯3図yv+−vt霧象I:姶り手r噴t(刺し団第4
図 19判1本に1 13uミq”rv−v 課−、i う#−“’rffi
’Jミi)嘔1!、1コ臣;[第5図 12bv退面 第6図 親半本体妖l 第1図 上 第8図
FIG. 1 is a diagram showing an embodiment of a mold for manufacturing a semiconductor device TJ according to the present invention, and FIG. 2 (A) is a plan view of a lead frame to which a semiconductor chip is fixed, which is sandwiched between the molds shown in FIG. 1. Figure 2 (B) and (C) are IIB-I in Figure 2 (A), respectively.
IB line, I Medium IV - IV line and ■
- A cross-sectional view taken along line v, Figure 6 is a diagram showing a mold constructed by sharing the middle and lower molds in Figure 1 and replacing only the upper mold, and Figure 7 shows the mold in Figure 6. A perspective view of a semiconductor device manufactured by a mold. FIG. 8 is a diagram showing a conventional mold for manufacturing semiconductor devices. In the figure, 10.21 is an upper mold for manufacturing semiconductor devices, 11.2
3 is the upper mold, 11a, 12a, 23a are the butting surfaces, 11b, 11c
, 23b is a recess, 12 is a lower die, 12b is a flat surface, 13.14 is a cavity, 15 is a semiconductor chip, 16 is a lead frame, 18.22 is a resin package, and 19.20 is a semiconductor device. 10 prison number 1 for knitting 14 = -1 し) zu = pi viewing L 19 cattle production amount CB) ), -11C (C) (A) Mine 3 figure yv + -vt mist elephant I: 喯Hand blow (Sashidan No. 4)
Figure 19 1 book contains 1 13u miq"rv-v division-, iu#-"'rffi
'Jmii) vomit 1! , 1 retainer; [Fig.

Claims (1)

【特許請求の範囲】 半導体チップをこれが固着されたリードフレームと共に
樹脂封止する一対の型よりなる半導体装置製造用モール
ド金型において、 該一対の型のうち、一方の型(11、23)のみにその
突き合せ面(11a、23a)に凹部(11b、11c
、23b)を形成し、 他方の型(12)は、その突き合せ面(12a)を実質
上平坦面(12b)とした構成を特徴とする半導体装置
製造用モールド金型。
[Scope of Claims] In a semiconductor device manufacturing mold consisting of a pair of dies for resin-sealing a semiconductor chip together with a lead frame to which the semiconductor chip is fixed, only one of the pair of dies (11, 23) is used. The abutting surfaces (11a, 23a) are provided with recesses (11b, 11c).
, 23b), and the other mold (12) is characterized in that its abutting surface (12a) is a substantially flat surface (12b).
JP16025586A 1986-07-08 1986-07-08 Molding die for manufacturing semiconductor device Pending JPS6315431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16025586A JPS6315431A (en) 1986-07-08 1986-07-08 Molding die for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16025586A JPS6315431A (en) 1986-07-08 1986-07-08 Molding die for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS6315431A true JPS6315431A (en) 1988-01-22

Family

ID=15711048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16025586A Pending JPS6315431A (en) 1986-07-08 1986-07-08 Molding die for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS6315431A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06280464A (en) * 1993-03-29 1994-10-04 Toyo Kensetsu Kk Method and device for inserting an underwater excavator for vertical holes
US6000924A (en) * 1996-01-24 1999-12-14 Cornell Research Foundation, Inc. Pressurized underfill encapsulation of integrated circuits
US6146919A (en) * 1997-07-09 2000-11-14 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06280464A (en) * 1993-03-29 1994-10-04 Toyo Kensetsu Kk Method and device for inserting an underwater excavator for vertical holes
US6000924A (en) * 1996-01-24 1999-12-14 Cornell Research Foundation, Inc. Pressurized underfill encapsulation of integrated circuits
US6146919A (en) * 1997-07-09 2000-11-14 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6188021B1 (en) 1997-07-09 2001-02-13 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6213747B1 (en) * 1997-07-09 2001-04-10 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6265660B1 (en) 1997-07-09 2001-07-24 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6537051B2 (en) 1997-07-09 2003-03-25 Micron Technology, Inc. Encapsulation mold with a castellated inner surface
US6899534B2 (en) 1997-07-09 2005-05-31 Micron Technology, Inc. Mold assembly for a package stack via bottom-leaded plastic (blp) packaging
US7094046B2 (en) 1997-07-09 2006-08-22 Micron Technology, Inc. Mold assembly for a package stack via bottom-leaded plastic (BLP) packaging

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