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JPS63152155A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS63152155A
JPS63152155A JP30067486A JP30067486A JPS63152155A JP S63152155 A JPS63152155 A JP S63152155A JP 30067486 A JP30067486 A JP 30067486A JP 30067486 A JP30067486 A JP 30067486A JP S63152155 A JPS63152155 A JP S63152155A
Authority
JP
Japan
Prior art keywords
sio2
oxide film
si3n4
film
element isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30067486A
Other languages
Japanese (ja)
Inventor
Yoichi Tatewaki
帯刀 洋一
Mitsuhiro Tsubakiyama
椿山 光宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP30067486A priority Critical patent/JPS63152155A/en
Publication of JPS63152155A publication Critical patent/JPS63152155A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To reduce an element isolation region and simultaneously prevent generation of damage in a substrate, by performing selective oxidation after forming the offset of an Si3N4 film wherein an SiO thin film is formed for an Si substrate. CONSTITUTION:An SiO2 12, and Si3N4 13 and an SiO2 14 are stacked on a P-type Si substrate 11. A mask is formed, RIE is performed, an SiO2 thin film 15 is arranged, and an Si3N4 thin film 16 and an SiO2 film 17 are deposited. Then a sidewall 17' of SiO2 is formed by RIE, and the Si3N4 16 and the SiO2 15 are eliminated by etching. The SiO2 14 and the sidewall 17' are subjected to wet etching, and an offset 16' of the Si3N4 film is formed. Thus an offset of Si3N4 is formed which has the SiO2 thin film 15 as a buffer layer arround a prearranged element isolation region. After a P-type inversion protection layer 18 is formed by implanting ions, a field oxide film 19 is formed by wet oxidation. By this constitution, the element isolation region can be reduced, and damages do not generate in the substrate.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置の製造方法に係り、特に、選択酸化
による微細な素子分離領域の形成方法に関するものであ
る。更に述べるならば、本発明は、バーズビーク伸長抑
制のための、シリコン窒化膜から成るオフセソIf設け
る構成の素子分離領域形成方法の改良に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a fine element isolation region by selective oxidation. More specifically, the present invention relates to an improvement in a method for forming an element isolation region in which an offset If made of a silicon nitride film is provided to suppress the extension of a bird's beak.

〈従来の技術〉 第2図(a)〜(e)は従来の製造方法の主要工程段階
に於ける状態全示す断面図である。
<Prior Art> FIGS. 2(a) to 2(e) are sectional views showing all the main process steps of a conventional manufacturing method.

シリコン基板1上に熱酸化膜2を形成した後、シリコン
窒化@3、シリコン酸化膜4を順次堆積し、マスク形成
、反応性イオンエツチングにより、素子領域予定領域上
に、熱酸化膜2、シリコン窒化膜3、シリコン酸化膜4
のパターンを形成する(第2図(a))。続いて、薄い
シリコン窒化膜5、シリコン酸化膜6′f:堆積する(
第2図(b) )。反応性イオンエツチングにより素子
領域予定領域周辺にシリコン酸化膜のサイドウオール6
′を形成し、続いて、このサイドウオール6′及びシリ
コン酸化膜4にマスクとしてシリコン窒化膜5テエノチ
ングする(第2図(C))。シリコン酸化膜4とシリコ
ン酸化膜のサイドウオール6′ヲウエノトエノチングに
より除去し、シリコン窒化膜のオフセット5′ヲ形成す
る(第2図(d))。この結果、素子分離予定領域の周
囲にシリコン窒化膜のオフセットが形成された状態とな
る。しかる後、スチーム雰囲気中で選択酸化全行ない、
フィールド酸化膜7を形成する(第2図(e))。
After forming a thermal oxide film 2 on a silicon substrate 1, a silicon nitride film 3 and a silicon oxide film 4 are sequentially deposited, and by mask formation and reactive ion etching, the thermal oxide film 2 and silicon Nitride film 3, silicon oxide film 4
A pattern is formed (FIG. 2(a)). Subsequently, a thin silicon nitride film 5 and a silicon oxide film 6'f are deposited (
Figure 2(b)). A silicon oxide film sidewall 6 is formed around the planned device area by reactive ion etching.
Then, the silicon nitride film 5 is etched on the sidewall 6' and the silicon oxide film 4 as a mask (FIG. 2(C)). The silicon oxide film 4 and the silicon oxide film sidewall 6' are removed by etching, and the silicon nitride film offset 5' is formed (FIG. 2(d)). As a result, an offset of the silicon nitride film is formed around the intended element isolation region. After that, selective oxidation is carried out in a steam atmosphere.
A field oxide film 7 is formed (FIG. 2(e)).

−〈発明が解決しようとする問題点〉 しかしながら、上記従来の製造方法には以下に示す問題
点がめった。すなわち、従来の方法では、素子分離領域
端の形状が急峻になり、基板に損傷が生じ易いという問
題点があった。
-<Problems to be Solved by the Invention> However, the above-mentioned conventional manufacturing method has encountered the following problems. That is, in the conventional method, the edge of the element isolation region has a steep shape, and the substrate is easily damaged.

本発明は上記問題点を解決することを目的としているも
のであり、素子分離領域幅を縮小しながらも、適度のバ
ーズビークを形成させ、これによって、素子分離領域端
の形状?緩やかにし、損傷発生の低減化を達成した半導
体装置製造方法全提供するものである。
The present invention is aimed at solving the above-mentioned problems, and forms an appropriate bird's beak while reducing the width of the element isolation region, thereby improving the shape of the edge of the element isolation region. The present invention provides a method for manufacturing a semiconductor device that is gentle and reduces the occurrence of damage.

く問題点を解決するための手段〉 その下面、すなわち、シリコン基板との間に薄いシリコ
ン酸化膜を有する、シリコン窒化膜のオフセノIf形成
し、その後、選択酸化を行なって素子分離領域を形成す
る。
Means for Solving Problems〉 A silicon nitride film with a thin silicon oxide film is formed on its lower surface, that is, between it and the silicon substrate, and then selective oxidation is performed to form an element isolation region. .

く作 用〉 上記溝底とすることにより、適度のバーズビークが形成
され、素子分離領域端の形状が緩やかになる。
Effect> By forming the groove bottom as described above, an appropriate bird's beak is formed, and the shape of the edge of the element isolation region becomes gentle.

〈実施例〉 以下、実施例に基づいて本発明の詳細な説明する。<Example> Hereinafter, the present invention will be described in detail based on examples.

第1図(a)〜(g)は本発明の一実施例の主要工程段
階に於ける状態を示す断面図である。
FIGS. 1(a) to 1(g) are cross-sectional views showing the main process steps of an embodiment of the present invention.

まず、P型シリコン基板lI上に熱酸化膜I2を形成し
た後、シリコン窒化膜13、シリコン酸化膜14を順次
堆積・する(第1図(a) )。続いて、マスク形成、
反応性イオンエツチングにより、素子領域予定領域上に
、熱酸化膜12、シリコン窒化膜13及びシリコン酸化
膜14のパターンを形成する(第1図(b))。次いで
、薄い熱、酸化膜15を形成し、薄いシリコン窒化膜1
6、シリコン酸化膜17を堆積する(第1図(C))。
First, a thermal oxide film I2 is formed on a P-type silicon substrate II, and then a silicon nitride film 13 and a silicon oxide film 14 are sequentially deposited (FIG. 1(a)). Next, mask formation,
A pattern of a thermal oxide film 12, a silicon nitride film 13, and a silicon oxide film 14 is formed on the intended device region by reactive ion etching (FIG. 1(b)). Next, a thin thermal oxide film 15 is formed, and a thin silicon nitride film 1 is formed.
6. Deposit a silicon oxide film 17 (FIG. 1(C)).

反応性イオンエツチングにより素子領域予定領域の周辺
にシリコン酸化膜のサイドウオール17′ヲ形成する(
第1図(d))。続いて、シリコン酸化膜のサイドウオ
ール17′とシリコン酸化膜14をマスクとして、シリ
コン窒化膜16と薄い熱酸化膜15をエツチングする(
第1図(e〕)。絖いて、シリコン酸化膜I4とシリコ
ン酸化膜のサイドウオール17′をウェットエツチング
により除去し、シリコン窒化膜のオフセット+6’4形
成する(第1図(f))。この結果、素子分離予定領域
の周囲に、薄い熱酸化膜I5をパック7層として持つシ
リコン窒化膜のオフセットが形成される。途中、第1図
(e)の段階で、フィールド反転防止のために、不純物
、例えばIIB+をイオン注入する(18:P型反転防
止層)しかる後、スチーム雰囲気中で選択酸化全行い、
フィールド酸化膜19を形成する(第1図(g))。
A silicon oxide film sidewall 17' is formed around the intended device area by reactive ion etching (
Figure 1(d)). Next, using the silicon oxide film sidewall 17' and the silicon oxide film 14 as masks, the silicon nitride film 16 and the thin thermal oxide film 15 are etched (
Figure 1 (e). Then, the silicon oxide film I4 and the silicon oxide film sidewall 17' are removed by wet etching, and an offset +6'4 silicon nitride film is formed (FIG. 1(f)). As a result, an offset of the silicon nitride film having the thin thermal oxide film I5 as the pack 7 layer is formed around the intended element isolation region. During the process, in the step shown in FIG. 1(e), impurities such as IIB+ are ion-implanted to prevent field inversion (18: P-type inversion prevention layer), and then selective oxidation is carried out in a steam atmosphere.
A field oxide film 19 is formed (FIG. 1(g)).

以下、図示しないが通常の工程に従い、フィールド酸化
膜19で囲まれた素子領域に素子を形成して半導体装置
を形成する。
Thereafter, elements are formed in the element region surrounded by the field oxide film 19 to form a semiconductor device according to normal steps (not shown).

〈発明の効果〉 以上詳細に説明したように、本発明の半導体装置製造方
法は、シリコン基板との間に薄いシリコン酸化膜を有す
るオフセラ)k形成した後、選択酸化を行って、素子分
離領域を形成するようにしたことを特徴とするものであ
り、本発明によれば、素子分離領域の縮小化を達成でき
ると同時に、基板中の損傷発生も防止することができる
、きわめて有用な半導体装置製造方法を提供することが
できるものである。
<Effects of the Invention> As explained in detail above, the method for manufacturing a semiconductor device of the present invention involves forming a thin silicon oxide film between a silicon substrate and then performing selective oxidation to form an element isolation region. According to the present invention, there is provided an extremely useful semiconductor device that can reduce the size of the element isolation region and at the same time prevent the occurrence of damage in the substrate. It is possible to provide a manufacturing method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(g)は本発明に係る素子分離領域形
成工程を工程順に示す断面図、第2回軸)乃至(e)は
従来の素子分離領域形成工程を工程順に示す断面コ 図
である。 符号の説明 +1:P型シリコン基板、12:熱酸化膜、13・シリ
コン窒化膜、14:シリコン酸化膜、+5:薄い熱酸化
膜、16:薄いシリコン窒化膜、16’ニジIJコン窒
化膜のオフセラ)、+7:ンIJコン酸化膜、17′:
シリコン酸化膜のサイドウオール、18:P型反転防止
層、+9:フィールド酸化膜。
1(a) to (g) are cross-sectional views showing the element isolation region forming process according to the present invention in process order, and FIGS. 1(a) to (e) are cross-sectional views showing the conventional element isolation area forming process in process order. It is a diagram. Explanation of symbols: +1: P-type silicon substrate, 12: thermal oxide film, 13. silicon nitride film, 14: silicon oxide film, +5: thin thermal oxide film, 16: thin silicon nitride film, 16' rainbow IJ-con nitride film. +7: IJ con oxide film, 17':
Sidewall of silicon oxide film, 18: P-type anti-inversion layer, +9: field oxide film.

Claims (1)

【特許請求の範囲】[Claims] 1、シリコン窒化膜から成るオフセットを形成した後、
選択酸化を行なって素子分離用フィールド酸化膜を形成
する、半導体装置の製造方法に於いて、上記オフセット
とシリコン基板との間に薄いシリコン酸化膜を設ける構
成としたことを特徴とする、半導体装置の製造方法。
1. After forming an offset made of silicon nitride film,
A semiconductor device manufacturing method in which a field oxide film for element isolation is formed by selective oxidation, characterized in that a thin silicon oxide film is provided between the offset and the silicon substrate. manufacturing method.
JP30067486A 1986-12-16 1986-12-16 Manufacture of semiconductor device Pending JPS63152155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30067486A JPS63152155A (en) 1986-12-16 1986-12-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30067486A JPS63152155A (en) 1986-12-16 1986-12-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63152155A true JPS63152155A (en) 1988-06-24

Family

ID=17887706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30067486A Pending JPS63152155A (en) 1986-12-16 1986-12-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63152155A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03156957A (en) * 1989-11-15 1991-07-04 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5068202A (en) * 1988-12-15 1991-11-26 Sgs-Thomson Microelectronics S.R.L. Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures
US5173444A (en) * 1990-09-18 1992-12-22 Sharp Kabushiki Kaisha Method for forming a semiconductor device isolation region
US7192840B2 (en) 2002-10-30 2007-03-20 Oki Electric Industry Co., Ltd. Semiconductor device fabrication method using oxygen ion implantation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068202A (en) * 1988-12-15 1991-11-26 Sgs-Thomson Microelectronics S.R.L. Process for excavating trenches with a rounded bottom in a silicon substrate for making trench isolation structures
JPH03156957A (en) * 1989-11-15 1991-07-04 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5173444A (en) * 1990-09-18 1992-12-22 Sharp Kabushiki Kaisha Method for forming a semiconductor device isolation region
US7192840B2 (en) 2002-10-30 2007-03-20 Oki Electric Industry Co., Ltd. Semiconductor device fabrication method using oxygen ion implantation

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