JPS63150941A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63150941A JPS63150941A JP29846486A JP29846486A JPS63150941A JP S63150941 A JPS63150941 A JP S63150941A JP 29846486 A JP29846486 A JP 29846486A JP 29846486 A JP29846486 A JP 29846486A JP S63150941 A JPS63150941 A JP S63150941A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- interlayer insulating
- insulating film
- protective film
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims abstract description 64
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 19
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法、特にオーバーエッチを
防止したコンタクトホールの形成を行う半導体装置の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which contact holes are formed while preventing overetching.
（ロ）従来の技術
従来の多層配線を有する半導体装置の製造方法を第２図
Ａ乃至第２図りを参照して詳述する。なお斯る従来技術
は特開昭６０−１５３１３１号公報等で知られている。(B) Prior Art A conventional method for manufacturing a semiconductor device having multilayer wiring will be described in detail with reference to FIGS. 2A to 2D. Incidentally, such a conventional technique is known from Japanese Patent Application Laid-Open No. 153131/1983.
先ず第２図Ａに示すように、所望のＭＯＳ）−ランジス
タ等を形成した半導体基板（１１）上に熱酸化によりゲ
ート酸化膜等を構成するシリコン酸化膜（１２）を付着
し、その上にリンドープしたポリシリコン層（１３）を
全面に付着する。このポリシリコン層（１３）は多層配
線を形成する第１の電極層（１５〉となる部分上をレジ
スト層（１４）で被覆する。First, as shown in FIG. 2A, a silicon oxide film (12) constituting a gate oxide film, etc. is deposited by thermal oxidation on a semiconductor substrate (11) on which desired MOS transistors, etc. are formed, and then A phosphorous-doped polysilicon layer (13) is deposited over the entire surface. A portion of this polysilicon layer (13) that will become a first electrode layer (15> forming a multilayer interconnection) is covered with a resist layer (14).
次に第２図Ｂに示すように、ポリシリコンＭ（１３）を
レジスト層（１４）をマスクとしてエツチングし、所望
のパターンを有する第１の電極ｆｆ（１５）を形成する
。エツチング方法としては周知のウェットエツチングあ
るいはＲＩＥ等のドライエツチングで達成できる。Next, as shown in FIG. 2B, the polysilicon M (13) is etched using the resist layer (14) as a mask to form a first electrode ff (15) having a desired pattern. The etching method can be achieved by well-known wet etching or dry etching such as RIE.
更に第２図Ｃに示すように、第１の電極層（１５）を被
覆し平坦な上面を有する層間絶縁膜（１６）を付着する
。層間絶縁膜（１６）としてはリンドープしたＰＳＧ膜
を用い、酸化膜（１２）上に約１４０００人の厚みにＣ
ＶＤ法で付着して上面の平坦化を行う。この結果、第１
の電極層（１５）上には約７０００人の厚みに付着され
る。Furthermore, as shown in FIG. 2C, an interlayer insulating film (16) covering the first electrode layer (15) and having a flat upper surface is deposited. A phosphorus-doped PSG film is used as the interlayer insulating film (16), and a carbon dioxide film is applied to a thickness of about 14,000 on the oxide film (12).
It is deposited using the VD method and the top surface is flattened. As a result, the first
The electrode layer (15) is deposited to a thickness of approximately 7000 nm.
更に第２図りに示すように、層間絶縁膜（１６）上を選
択的にレジスト層（１７）で被覆した後、第１の電極層
（１５）上と半導体基板（１１〉上に複数のコンタクト
孔（１８）を形成する。本工程はＭＯＳトランジスタの
シリコンゲート電極とソースドレイン電極を形成すると
きに適用され、レジスト層（１７）をマスクとして層間
絶縁膜（１６）をＲＩＥ等のドライエツチングでエツチ
ングしてコンタクト孔（１８）を形成している。Further, as shown in the second diagram, after selectively covering the interlayer insulating film (16) with a resist layer (17), a plurality of contacts are formed on the first electrode layer (15) and the semiconductor substrate (11>). A hole (18) is formed. This step is applied when forming a silicon gate electrode and a source/drain electrode of a MOS transistor, and the interlayer insulating film (16) is dry etched by RIE or the like using the resist layer (17) as a mask. A contact hole (18) is formed by etching.
くハ）発明が解決しようとする問題点
しかしながら、斯上した従来の半導体装置の製造方法で
は、第１の電極層（１５）上と半導体基板（１１）上と
では表面の平坦化を行うため層間絶縁膜（１６）の厚み
が異なる。具体的には、半導体基板（１１）上には約１
４０００人となり、第１の電極層（１５）上では約７０
００人となる。従ってコンタクト孔（１８）を同時にエ
ツチングすると、第１の電極Ｍ（１５）上に早くコンタ
クト孔（１８）が形成され、半導体基板（１１）までコ
ンタクト孔（１８）が形成されるまで第１０′）電極層
（１５）がオーバーエツチングされる。このため第１の
電極層（１５）が薄くなりその抵抗値が増加したり、第
１の電極層（１５）にダメージが増加する問題点を有し
ていた。C) Problems to be Solved by the Invention However, in the conventional semiconductor device manufacturing method described above, the surfaces of the first electrode layer (15) and the semiconductor substrate (11) are flattened. The thickness of the interlayer insulating film (16) is different. Specifically, about 1 on the semiconductor substrate (11)
4,000 people, and about 70 people on the first electrode layer (15)
00 people. Therefore, if the contact hole (18) is etched at the same time, the contact hole (18) is quickly formed on the first electrode M (15), and the contact hole (18) is etched until the contact hole (18) is etched up to the semiconductor substrate (11). ) The electrode layer (15) is overetched. For this reason, there were problems in that the first electrode layer (15) became thinner, its resistance value increased, and damage to the first electrode layer (15) increased.
（ニ）問題点を解決するための手段
本発明は斯る問題点に鑑みてなされ、第１の電極層上面
を層間絶縁膜よりエツチング速度の遅い保護膜で被覆し
て第１の電極層のオーバーエツチングを防止して従来の
問題点を大巾に改善した半導体装置の製造方法を実現し
ている。(d) Means for Solving the Problems The present invention has been made in view of the above problems, and the upper surface of the first electrode layer is covered with a protective film whose etching rate is slower than that of the interlayer insulating film. A method of manufacturing a semiconductor device has been realized which greatly improves the conventional problems by preventing over-etching.
（＊）作用
本発明に依れば、第１の電極層上に付着した保護膜のエ
ツチング速度を層間絶縁膜のエツチング速度より遅く設
定することにより、コンタクト孔が第１の電極層から半
導体基板に達するまで時間中保護膜で第１の電極層が保
護されているので、第１の電極層のオーバーエツチング
は防止される。(*) Effect According to the present invention, by setting the etching rate of the protective film deposited on the first electrode layer to be slower than the etching rate of the interlayer insulating film, the contact hole is formed from the first electrode layer to the semiconductor substrate. Over-etching of the first electrode layer is prevented since the first electrode layer is protected by the protective film during the etching period.
（へ）実施例
本発明の一実施例を第１図Ａ乃至第１図Ｆを参照して詳
述する。(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1F.
先ず第１図Ａに示すように、所望のＭＯＳ）−ランジス
タ等を形成した半導体基板（１）上に熱酸化によりゲー
ト酸化膜等を構成するシリコン酸化膜（２）を付着し、
その上にリンドープしたポリシリコン層（３）を全面に
付着し、更に本発明の特徴とする保護膜（４）をポリシ
リコン層（３）上に全面に付着している。First, as shown in FIG. 1A, a silicon oxide film (2) constituting a gate oxide film, etc. is deposited by thermal oxidation on a semiconductor substrate (1) on which desired MOS transistors, etc. are formed.
A phosphorus-doped polysilicon layer (3) is deposited on the entire surface, and a protective film (4), which is a feature of the present invention, is further deposited on the entire surface of the polysilicon layer (3).
ポリシリコン層（３）は第１の電極層（６）を形成する
もので、周知の減圧ＣＶＤ法により厚さ５０００〜６０
００人に付着し、その表面にプラズマＣＶＤ法により約
１０００人のシリコン窒化膜（ＳＩＮ）（４）を付着す
る。更に保護膜（４）上には多層配線を形成する第１の
電極層（６）となるパターンで選択的にレジスト層（５
）で被覆する。なおポリシリコン層（３）の代りにアル
ミニウム等のスパッタ１こよる金属材料で第１の電極層
（６）を形成しても良い。The polysilicon layer (3) forms the first electrode layer (6) and is formed to a thickness of 5,000 to 60 nm by the well-known low pressure CVD method.
A silicon nitride film (SIN) (4) of approximately 1,000 layers is deposited on the surface thereof by plasma CVD. Furthermore, a resist layer (5) is selectively formed on the protective film (4) in a pattern that will become the first electrode layer (6) forming the multilayer wiring.
). Note that instead of the polysilicon layer (3), the first electrode layer (6) may be formed of a sputtered metal material such as aluminum.
次に第１図Ｂに示すように、ポリシリコン層（３）およ
び保護膜（４）をレジスト層（５）をマスクとしてエツ
チングし、所望のパターンを有する保護膜（４）で被覆
された第１の電極層（６）を形成する。Next, as shown in FIG. 1B, the polysilicon layer (3) and the protective film (4) are etched using the resist layer (5) as a mask. 1 electrode layer (6) is formed.
エツチング方法としては周知のウェットエツチングある
いはＲＩＥ等のドライエツチングを用いる。なお第１の
電極層（６）は約６０００人の段差を形成する。As the etching method, well-known wet etching or dry etching such as RIE is used. Note that the first electrode layer (6) forms a step difference of about 6000 people.
更に第１図Ｃに示すように、第１の電極層（６）を被覆
し平坦な上面を有する層間絶縁膜（７）を付着する。層
間絶縁膜（７）としてはリンドープしたＰＳＧ膜を用い
、シリコン酸化膜（２）上に約１４０００人の厚みに減
圧ＣＶＤ法で付着して上面の平坦化を実現する。この結
果、第１の電極層（６）上には約７０００人の厚みに層
間絶縁膜（７〉が堆積される。Furthermore, as shown in FIG. 1C, an interlayer insulating film (7) covering the first electrode layer (6) and having a flat upper surface is deposited. A phosphorus-doped PSG film is used as the interlayer insulating film (7), and is deposited on the silicon oxide film (2) to a thickness of about 14,000 yen by low pressure CVD to achieve a planarized upper surface. As a result, the interlayer insulating film (7) is deposited on the first electrode layer (6) to a thickness of approximately 7000 mm.
更に第１図りおよび第１図Ｅに示すように、層間絶縁膜
（７）上を選択的にレジスト層（８）で被覆した後、第
１の電極層（６）上と半導体基板（１）上に複数のコン
タクト孔（９）を形成する。Furthermore, as shown in Figure 1 and Figure 1E, after selectively covering the interlayer insulating film (7) with a resist layer (8), the first electrode layer (6) and the semiconductor substrate (1) are coated. A plurality of contact holes (9) are formed on the top.
本工程はＭＯ８Ｉ−ランジスタのシリコンゲート電極と
ソースドレイン電極等を形成するときに適用され、レジ
スト層（８）をマスクとして層間絶縁膜（７）をＲＩＥ
等のドライエツチングによりコンタクト孔（９）を形成
している。第１図りはコンタクト孔（９）が第１の電極
層（６）上の保護膜（４）に達するまでの過程を示し、
複数のコンタクト孔（９）は均一のエツチング速度で同
じ深さだけ層間絶縁膜（７）をエツチングして形成され
る。第１図Ｅは本発明の特徴とするものであり、保護膜
（４）がエツチングされる間に層間絶縁膜（７）がエツ
チングされてコンタクト孔（９）が半導体基板（１）ま
で到達する様子を示している。即ち、層間絶縁膜（７）
は前述した如く、第１の電極Ｍ（６）上には約７０００
人、半導体基板（１）上には約１４０００人の厚みに堆
積されているので、第１図Ｅの状態では半導体基板（１
〉上には約７０００人の層間絶縁膜（７）が残存してい
る。５０１１１１１ Ｉ’ｏｒｒに減圧し、ＣＦ−０１
（８％）の雰囲気で８００Ｗの出力でＲＩＥを行うと、
ＰＳＧよりなる層間絶縁膜（７）は７００人／ｍｉｎの
エツチング速度となり、ＳＩＮよりなる保護膜（４）は
１００人／ｍｉｎのエツチング速度となり、保護膜（４
）の厚みを１０００人に設定すれば、第１の電極層（６
）上の保護膜（４）と基板（１）上の残存する層間絶縁
膜（７）はほぼ同時にエツチングを終了する。このため
第１の電極層（６）はエツチングされるおそれがなくな
る。This process is applied when forming the silicon gate electrode, source drain electrode, etc. of MO8I-transistor, and RIEs the interlayer insulating film (7) using the resist layer (8) as a mask.
A contact hole (9) is formed by dry etching. The first diagram shows the process until the contact hole (9) reaches the protective film (4) on the first electrode layer (6),
A plurality of contact holes (9) are formed by etching the interlayer insulating film (7) to the same depth at a uniform etching rate. FIG. 1E shows a feature of the present invention, in which the interlayer insulating film (7) is etched while the protective film (4) is being etched, and the contact hole (9) reaches the semiconductor substrate (1). It shows the situation. That is, the interlayer insulating film (7)
As mentioned above, there are about 7000 on the first electrode M(6).
The semiconductor substrate (1) is deposited to a thickness of about 14,000 people, so in the state shown in Figure 1E, the semiconductor substrate (1) is
> Approximately 7,000 interlayer insulating films (7) remain on the surface. 5011111 Reduce pressure to I'orr and CF-01
When performing RIE with an output of 800W in a (8%) atmosphere,
The interlayer insulating film (7) made of PSG has an etching rate of 700 people/min, and the protective film (4) made of SIN has an etching rate of 100 people/min.
) is set to 1000, the thickness of the first electrode layer (6
) and the remaining interlayer insulating film (7) on the substrate (1) are finished etching almost simultaneously. Therefore, there is no fear that the first electrode layer (6) will be etched.
更に第１図Ｆに示すように、居間絶縁膜（７）上に第２
の電極層（１０）を形成するアルミニウム等の金属材料
をスパッタにより付着する。第２の電極層（１０）はコ
ンタクト孔（９）内にも付着され、半導体基板り１）お
よび第１の電極層（６）と接続される。Furthermore, as shown in FIG. 1F, a second
A metal material such as aluminum forming the electrode layer (10) is deposited by sputtering. A second electrode layer (10) is also deposited in the contact hole (9) and is connected to the semiconductor substrate 1) and the first electrode layer (6).
（ト）発明の効果
本発明に依れば、第１の電極層（６）上を所定の厚みの
保護膜（４）で被覆することにより、平坦化した層間絶
縁膜（７）を用いても第１の電極層（６）のオーバーエ
ツチングが防止され、第１の電極層（６）のオーバーエ
ツチングによる抵抗値の上昇や接合不良を無くす利点を
有する。(G) Effects of the Invention According to the present invention, by covering the first electrode layer (6) with the protective film (4) of a predetermined thickness, the flattened interlayer insulating film (7) is used. This also has the advantage of preventing over-etching of the first electrode layer (6) and eliminating increases in resistance and poor bonding caused by over-etching of the first electrode layer (6).
また第１の電極層（６）表面へのイオンの衝撃も防止さ
れるので、ポリシリコン層の結晶のみだれによるコンタ
クト抵抗の上昇も防止できる利点を有する。Furthermore, since ion bombardment on the surface of the first electrode layer (6) is also prevented, there is an advantage that an increase in contact resistance due to crystal graining of the polysilicon layer can be prevented.
第１図Ａ乃至第１図Ｆは本発明による半導体装置の製造
方法を説明する断面図、第２図Ａ乃至第２図りは従来の
半導体装置の製造方法を説明する断面図である。
（１）は半導体基板、 （２〉はシリコン酸化膜、（３
）はポリシリコン層、 （４）は保護膜、 （５）（８
）はレジスト層、り６）は第１の電極層、 （７）は層
間絶縁膜、 （９）はコンタクト孔、 （１０）は第２
の電極層である。1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2A to 2F are sectional views illustrating a conventional method of manufacturing a semiconductor device. (1) is a semiconductor substrate, (2> is a silicon oxide film, (3)
) is a polysilicon layer, (4) is a protective film, (5) (8
) is the resist layer, 6) is the first electrode layer, (7) is the interlayer insulating film, (9) is the contact hole, (10) is the second
This is the electrode layer.
Claims (1)
なる第１の電極層を形成する工程と前記第１の電極層を
被覆し平坦な上面を有する層間絶縁膜を付着する工程と
前記層間絶縁膜を貫通し前記第１の電極層および前記半
導体基板に達する複数のコンタクト孔を形成する工程と
を具備する半導体装置の製造方法において、前記第１の
電極層上面に前記層間絶縁膜よりエッチング速度の遅い
保護膜を付着した後、前記コンタクト孔のエッチングを
行うことを特徴とする半導体装置の製造方法。(1) A step of forming a first electrode layer made of a semiconductor material or a metal material on a semiconductor substrate, a step of depositing an interlayer insulating film that covers the first electrode layer and has a flat upper surface, and the interlayer insulating film forming a plurality of contact holes penetrating through the first electrode layer and reaching the semiconductor substrate; A method for manufacturing a semiconductor device, characterized in that the contact hole is etched after depositing a slow protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29846486A JPH0727908B2 (en) | 1986-12-15 | 1986-12-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29846486A JPH0727908B2 (en) | 1986-12-15 | 1986-12-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63150941A true JPS63150941A (en) | 1988-06-23 |
| JPH0727908B2 JPH0727908B2 (en) | 1995-03-29 |
Family
ID=17860043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29846486A Expired - Lifetime JPH0727908B2 (en) | 1986-12-15 | 1986-12-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727908B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63296242A (en) * | 1987-05-27 | 1988-12-02 | Nec Corp | Manufacture of semiconductor device |
| JPH05226477A (en) * | 1992-02-17 | 1993-09-03 | Sharp Corp | Contact forming method |
| US5444020A (en) * | 1992-10-13 | 1995-08-22 | Samsung Electronics Co., Ltd. | Method for forming contact holes having different depths |
| JPH09266252A (en) * | 1996-03-28 | 1997-10-07 | Nec Corp | Semiconductor device manufacturing method |
| KR20000044955A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for fabricating contact hole |
| JP2010050474A (en) * | 2009-10-20 | 2010-03-04 | Fujitsu Microelectronics Ltd | Semiconductor device, and method of manufacturing the same |
| US9082820B2 (en) | 2012-09-28 | 2015-07-14 | Canon Kabushiki Kaisha | Manufacturing method of semiconductor apparatus |
| US9391112B2 (en) | 2012-09-28 | 2016-07-12 | Canon Kabushiki Kaisha | Semiconductor apparatus |
-
1986
- 1986-12-15 JP JP29846486A patent/JPH0727908B2/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63296242A (en) * | 1987-05-27 | 1988-12-02 | Nec Corp | Manufacture of semiconductor device |
| JPH05226477A (en) * | 1992-02-17 | 1993-09-03 | Sharp Corp | Contact forming method |
| US5444020A (en) * | 1992-10-13 | 1995-08-22 | Samsung Electronics Co., Ltd. | Method for forming contact holes having different depths |
| JPH09266252A (en) * | 1996-03-28 | 1997-10-07 | Nec Corp | Semiconductor device manufacturing method |
| KR20000044955A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for fabricating contact hole |
| JP2010050474A (en) * | 2009-10-20 | 2010-03-04 | Fujitsu Microelectronics Ltd | Semiconductor device, and method of manufacturing the same |
| US9082820B2 (en) | 2012-09-28 | 2015-07-14 | Canon Kabushiki Kaisha | Manufacturing method of semiconductor apparatus |
| US9391112B2 (en) | 2012-09-28 | 2016-07-12 | Canon Kabushiki Kaisha | Semiconductor apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727908B2 (en) | 1995-03-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |