JPS631478Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a radio receiver with a clock that selectively switches between a clock display and a frequency display on a display, and the present invention relates to a radio receiver with a clock that selectively displays a clock display and a frequency display. This invention relates to a radio receiver with a clock that displays frequency only during periods and displays time during other periods.

Here, a conventional clock radio receiver will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a circuit diagram of a main part of a conventional clock radio receiver.

In Figure 1, 1 is for display drive to display the reception frequency of the FM-AM receiver, and to display the time when the reception frequency does not need to be displayed.
It is an IC. In the IC 1, 2 is a frequency divider that divides the frequency of the local oscillation signal from the FM radio reception section, and 3 is a frequency divider that selectively divides the frequency of the signal from the frequency divider and the local oscillation signal from the AM radio reception section. Band switching circuit added to counter 4, 4' is IF OFFSET circuit,
5 is a latch circuit; 6 is a frequency fluctuation detection signal output terminal that is connected to the latch circuit 5 and outputs a pulse that detects a fluctuation when the frequency of the local oscillation signal from the radio receiving unit fluctuates; 7 is an attached clock crystal vibration 7' is a crystal oscillation circuit, 8 is a frequency divider that divides the signal from the crystal oscillation circuit, 9 is a clock counter that counts the signal from the frequency divider, and 10 is for switching the clock/frequency display. Control signal input terminal, 11
is a multiplexer to which signals from the latch circuit 5, clock counter 9, and clock/frequency display switching control signal input terminal 10 are input;
Using a control signal from the frequency display switching control signal input terminal 10, the output of the latch circuit 5 or clock counter 9 is selectively added to the display register 12, and the time or reception frequency is selectively displayed on the external display 13. digitally displayed. 14 is an external timer circuit connected to the frequency fluctuation detection signal output terminal 6, and the timer circuit includes a capacitor C,
and an integrating circuit 18 composed of resistors R ₁ and R ₂ ,
A phase inverting transistor Q whose base is connected to the integrating circuit and whose collector is connected to the clock/frequency display switching control signal input terminal 10, and a resistor connected between the power supply +B ₁ common to IC1 and the collector of the transistor Q. It is composed of R ₃ .

Next, the operation of the circuit shown in FIG. 1 will be explained.

When the frequency of the local oscillation signal from the radio receiving section fluctuates, such as when selecting a channel, a pulse that detects this fluctuation [Fig. 2 A] is sent from the frequency fluctuation detection signal output terminal 6, and the resistance _R1 and The integrating circuit 18 having a time constant due to the capacitor C is triggered to operate the integrating circuit. Then, the timer pulse obtained by the integrating circuit 18 (FIG. 2B) is invertedly shaped by the transistor Q and the resistor _R3 , and the invertedly shaped control signal [FIG. 2C] is
In addition to the clock/frequency display switching control signal input terminal 10 of IC 1, the reception frequency is displayed on the display 13 only during the period (period t ₁ ) when a low level signal (first control signal) is applied to the input terminal. Switch to digital display.

In other words, when a fluctuation occurs in the local oscillation frequency of the radio receiving section, a pulse is output from the detection signal output terminal 6, and the capacitor C and the resistor R ₁ of the integrating circuit 18
Transistor Q for a period of t ₁ due to the time constant
The potential applied to the base of the control signal input terminal 10 rises, and the control signal applied to the control signal input terminal 10 becomes low level for a period of _t1 , thereby entering the reception frequency display mode. During other periods, a high-level control signal (second control signal) is applied to the control signal input terminal 10, and the display 13 enters a time display mode in which the time is displayed. Therefore, at the moment when the power to the radio receiving section is turned on or off, the local oscillation signal of the radio receiving section is generated or disappears, so a pulse is generated from the frequency fluctuation detection signal output terminal 6, and the timer circuit 14 operates to enter the received frequency display mode. In this way, power to the radio receiver is
When it is turned OFF, the reception frequency display mode will be activated for the period _t1 from that moment, but since there is no local oscillation signal from the radio receiver during this period, the display 13 will display a meaningless value. It had the drawback of being stored away. The present invention proposes a clock radio receiver that eliminates such drawbacks, and one embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

In FIG. 3, the same parts as in FIG. 1 are designated by the same numbers as in FIG. 1.

In the circuit shown in FIG. 3, a diode D and a resistor _R4 are connected between the input terminal 6' of the timer circuit 14 and the movable terminal 16 of the power switch S of the radio receiver 15.
The present invention is characterized in that a reset circuit 17 consisting of a series circuit is provided.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to FIG. 4 as well.

From the current time display mode, if you turn off the power switch S of the radio receiving section 15 at time _t2 ,
The power supply + _B2 to the radio receiving section 15 falls as shown in FIG. 4B, and a pulse is generated at the detection signal output terminal 6 of the IC1, as shown in FIG.
The potential of the output terminal P of No. 8 tends to rise on the broken line in FIG. 4C. However, since the power supply +B ₂ drops, diode D becomes conductive in the forward direction, and the current from detection signal output terminal 6 flows from diode D to resistor R ₄
The potential at the output terminal P of the integrating circuit 18 does not rise as shown by the solid line in FIG. 4C, and the integrating timer circuit 14 is reset and does not work. Therefore, no low level signal is applied to the control signal input terminal 10, and the mode is not switched to the received frequency display mode. Also, when the power switch S of the radio receiving section 15 is turned off from the reception frequency display mode (the state where a low level signal is applied to the control input terminal 10 as shown by the dashed line in FIG. 4), , the potential at the output terminal P of the integrating circuit 18 falls at time _t2 , and a high-level signal is applied to the clock/frequency display switching control signal input terminal 10 as shown by the solid line in FIG. Switch to time display mode. In this way, in the circuit shown in FIG. 3, when the power switch S of the radio receiver 15 is turned off, the timer circuit 14 for switching the display mode is reset, and the display 1 is instantly turned off.
3 to switch to the mode that displays the time. Therefore, the power to the radio receiving section 15 is turned off.
It is possible to eliminate the drawback that meaningless display is performed on the display 13 for a predetermined period from the moment the display is turned on.

As described above, according to the clock radio receiver according to the present invention, malfunction of the display when the power to the radio receiving section is turned off can be prevented by simply adding a simple circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the main parts of a conventional clock radio receiver, and Figure 2 A, B, and C are timing charts showing voltage waveforms at each point of the circuit in Figure 1, with time on the horizontal axis. , the voltage is plotted on the vertical axis. Figure 3 is a circuit diagram showing the main parts of the clock radio receiver of the present invention;
4A, 4B, 4C and 4D are timing charts showing voltage waveforms at various points in the circuit of FIG. 3, with the horizontal axis representing time and the vertical axis representing voltage. DESCRIPTION OF SYMBOLS 1... Display drive IC, 6... Detection signal output terminal, 10... Control signal input terminal, 14... Timer circuit, 17... Reset circuit.

Claims (1)

[Scope of utility model registration request] A detection signal output terminal that outputs a detection signal obtained by detecting frequency fluctuations of a local oscillation signal from a radio receiving unit, and control for selectively switching whether to display a clock or a frequency on a display. a display device drive circuit having a control signal input terminal into which a signal is input, and a display device drive circuit connected between the detection signal output terminal and the control signal input terminal, and the display device drive circuit having a control signal input terminal to which a signal is input; In a radio receiver with a clock, the clock radio receiver is equipped with a timer circuit that applies a first control signal for frequency display only during the period and a second control signal for clock display during other periods, the input terminal of the timer circuit and the radio A reset circuit is provided between the receiver and the power switch, and when the power switch is turned off, the reset circuit resets the timer circuit, thereby causing the timer circuit to supply a second control signal to the control signal input terminal. What is claimed is: 1. A radio receiver with a clock, characterized in that the radio receiver is set to a state in which the clock is displayed on the display and the clock is displayed on the display.