JPS63146682A - Skew correction circuit for vtr - Google Patents

Abstract

PURPOSE:To attain skew correction almost not causing phase discontinuity of chrominance signal subcarrier with simple constitution by using a crystal oscillator so as to oscillate a frequency signal being 4 times the chrominance signal subcarrier frequency so as to use it as a clock of a CCD delay line, applying 1/4 frequency division to the signal so as to use it as a reference signal of an APC circuit of the reproduced color signal processing. CONSTITUTION:The crystal oscillator 18 is oscillated at a frequency being 4 times the chrominance signal subcarrier frequency. Then the output signal is inputted to a CCD delay line 19 giving a delay of 0.5H as a clock. Simultaneously, the output signal of the crystal oscillator 18 is subjected to 1/4 frequency division by a 1/4 frequency divider 20 and outputted as a signal of the chrominance signal subcarrier frequency. Moreover, the signal of the chrominance signal subcarrier frequency outputted form the 1/4 frequency divider 20 is inputted to a reproduced color signal processing circuit 7 and become a reference signal of a reproduced APC circuit. Thus, the phase of the subcarrier of the recovered chominance signal outputted from the recovered chrominance signal processing circuit is locked completely to the phase of the signal of the chrominance signal subcarrier frequency outputted from the 1/4 frequency divider 20. Moreover, the phase of the subcarrier wave of the reproduced color signal is locked to the phase of the clock signal inputted to the CCD delay line 19.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a VTR (video tape recorder) in which, when special playback is performed, the H arrangement of the track pattern of the tape, or the mounting position of the special playback head and the standard head is determined. For related purposes, the present invention relates to a circuit that corrects skew distortion occurring in a reproduced video signal.

Conventional technology In home VTRs, skew distortion has conventionally occurred in the following cases.

■ In the format of the track pattern on the tape,
When you perform search playback on items that are not aligned properly.

■ There are two types of playback modes: standard time playback mode and long-time playback mode, and due to the H arrangement of each track pattern, the installation position of the special playback head when performing field playback is compatible with both playback modes. (Differences: 0) Of the above, ■ corresponds to, for example, the 4-hour recording mode in a VH3 VTR. In the VHS 4-hour recording mode, αH (which indicates the H arrangement of the track pattern and indicates the deviation of the start positions of adjacent tracks in H units) is 0.76, so when searching and playing, it is difficult to cross tracks. A skew of 0.5 H occurs each time it is played.

■For example, in VH3VTR, standard recording mode (
This problem occurs when attempting to perform field playback using the special playback head during still and slow playback in both modes with a deck that can play back both 2-hour recording mode and 4-hour recording mode. In other words, in standard recording mode αH
is 1.5, so the special reproducing head must be installed at a distance of nH from the standard reproducing head on the pattern. On the other hand, in the 4-hour recording mode, αH is 0.75, so the special playback heads must be installed at a distance of (n + 0.25)H.Both of the above specifications cannot be satisfied with a single special playback head. 0.2 in field playback during slow and still playback in either mode
5H skew occurs.

Standard recording mode (2
In the long-time recording mode (4-hour recording), αH is 10, whereas in the long-term recording mode (4-hour recording), αH is 05.
For special playback, the mounting position of the do must be either (n+0.5)H or nH, and in either mode it is
, 5H skew occurs.

All of the above examples are for NTSC VTRs.

This is a description of the matte, and a different skew may occur in the PAL VTR format.

Now, when a skew occurs during such special playback, conventionally the reproduced signal is delayed by a delay line at the time when the skew occurs to correct the discontinuity of the reproduced signal due to the skew. FIG. 2 shows an example of a conventional skew correction circuit.

In the figure, 1, 2.3 are video heads;
Performs normal recording and playback. Further, since the home VTR performs azimuth recording, the nozzle 1 and the head 2 have different azimuth angles. Head 3 is a special reproduction head and has the same azimuth as head 1. In field reproduction during slow and still reproduction, head 1 and head 3 perform field reproduction.

As described above, the mounting position of the head 3 with respect to the head 2 is determined according to the arrangement and spacing of the H's on the track and cross patterns. Therefore, during normal playback, the switch SB5 is connected to the head 2 side, and the head S field signal input from the terminal 16 at the switch SA4 causes the head 1 and the head 2 to be connected.
Switch and output the output. On the other hand, during field playback during special playback, the switch SB5 is switched to the head 3 side in response to a special playback command signal from the terminal 16, and the switch SA
At step 4, the outputs of the heads 1 and 3 are switched and outputted by the head switch signal. The reproduced signal output from the switch SA4 is subjected to reproduction signal processing by the reproduced luminance signal processing circuit 6 and the reproduced color signal processing circuit 7, and the reproduced luminance signal and reproduced color signal obtained thereby are sent to the mixer 8.
switch 5C1 as a playback video signal.
1. Output to the output terminal 14 through the output buffer 13. Reference numeral 17 denotes a skew correction circuit which operates if skew occurs during special playback. For example, in the case of 8mm video,
When the mounting positions of head 2 and head 3 are set to nH (
Normally 2H) In long-time mode playback, no skew occurs even in field playback during special playback, but in standard mode playback, skew occurs by 0.6H when field playback is performed.
skew occurs.

Therefore, in this case, a skew detection signal is created by the gate circuit 12 from the special reproduction command signal and the head switch signal inputted from the terminals 15 and 16, and when a skew occurs, the switch 5C11 is switched based on the detection signal and the 0.5H delay line 9 is and outputs the reproduced video signal that has passed through the low-pass filter 1o. In this way, when a skew occurs, it corresponds to the amount of the skew. , sH, and then outputs the reproduced video signal to correct the skew. Note that the 0.5H delay line 9 is generally a glass delay line or a CCD Charge Coup.
A ledDevice delay line is used. In the case of a glass delay line, low frequency signals do not pass through, so the video signal is
AM modulation is performed using a carrier of about 0 MHz, the modulated video signal is delayed by a glass delay line, and then AM demodulation is performed to obtain a delayed video signal. In addition, the low-pass filter 1o removes unnecessary noise and clock signals mixed in by passing through the shH delay line 9.
This is used to remove carrier signals and the like.

An example of such a conventional technique is described, for example, on page 25 of the September 1985 issue of Television Engineering Magazine.

Problems to be Solved by the Invention However, in the conventional configuration as described above, a luminance signal and a chrominance signal are mixed as a reproduced video signal and the chrominance signal is mixed at the same time.
Since the skew is corrected by switching with a delay of there were. This is because there is some variation in the delay time of the 11io and tsH delay lines. The color signal subcarrier is NTS
In C, one cycle is about 280 nS. On the other hand, conventional delay lines, whether glass delay lines or CCD delay lines, have several tens of thousands of
The delay time of nS has some fluctuations. Generally, the subcarrier of the color signal has a phase of about 6° (approximately 4nS) in NTSC.
), the hue variation becomes unacceptable. Since the above-described skew correction circuit corrects the skew that occurs at the time of head switching, the skew occurs and is corrected several H before the vertical synchronization signal. Therefore, even if a phase shift occurs in the subcarrier of the chrominance signal at that point, the television signal will be displayed within the vertical blanking period until the chrominance signal begins:
If the APC circuit on the I side sufficiently absorbs this phase shift of the subcarrier, no hue fluctuation will occur on the television screen.

However, since the APC circuit of a television has a slow response, if there is a phase shift of several tens of degrees (several tens of nanoseconds), hue fluctuations will appear on the television screen.

Furthermore, in the conventional configuration, a low-pass filter is passed after the delay line, but since this low-pass filter also has group delay characteristics, it causes a delay in the video signal passing through it.

Therefore, in the conventional delay line, the regular delay time of the delay line is reduced by the delay time of this low-pass filter. In this way, since the delay time is determined by the sum of both the delay time due to the delay line and the delay time due to the low-pass filter, the variation in the delay time is due to not only the variation in the delay time of the delay line but also the delay time due to the low-pass filter. This is also related to the variation in delay time.

Therefore, although conventional skew correction circuits can correct the skew of the reproduced video signal, they cannot avoid the phase discontinuity of the subcarrier of the color signal, and a certain degree of compromise must be made with respect to hue fluctuations in the television image caused by this. The situation was impossible.

Note that the following skew circuit can be considered as a skew circuit that does not cause such phase discontinuity of subcarriers of color signals. In other words, the chrominance signal is demodulated into two baseband chrominance signals, the two baseband chrominance signals and luminance signals are each delayed separately, and then the undelayed original signal and the skewed original signal are separated. Then, the two baseband color signals that have been corrected for skew are subjected to quadrature two-phase modulation to obtain the original modulated color signal, and by mixing this with the ski-corrected luminance signal, the skew is corrected. The objective is to obtain a reproduced video signal that has no discontinuity in subcarrier phase. However, such a configuration requires as many as three delay lines and a color signal modulator/demodulator, resulting in a very high cost.

In view of this problem, the present invention provides a skew correction circuit that has a simple configuration and hardly generates phase discontinuity in color signal subcarriers.

Means for Solving the Problems The present invention provides a crystal oscillator that oscillates at a frequency four times the color signal subcarrier frequency, a frequency divider that divides the output signal of the crystal oscillator by %, and an output of the frequency divider. An automatic phase control circuit that controls the carrier wave phase of the reproduced color signal to be phase-locked to the signal, a so-called APC circuit, an adder that mixes the reproduced color signal and the reproduced luminance signal that are output from the APC circuit, and the crystal oscillator. a CCD delay line which uses the output signal of the adder as a clock and inputs and delays the reproduced video signal which is the output of the adder; and the output signal of the adder and the output signal of the CCD delay line according to occurrence of skew. This skew correction circuit includes a switch circuit that performs switching and outputs.

It goes without saying that the delay time of the CCD delay line corresponds to the amount of skew, but if the period of the clock is τ, then the delay time is (4a n
φτ).

According to the above structure, the delay time of the CCD delay line is managed by the stable lock obtained by the crystal oscillator.
, and the AP of the reproduction color signal processing so that the subcarrier phase of the reproduction color signal is locked to the signal obtained by dividing the clock by A.
Since the C circuit is activated, the subcarrier phase of the reproduced color signal input to the CCD delay line is synchronized with the clock. In other words, four clock pulses are always input in synchronization with one cycle of the subcarrier of the input reproduced color signal.

The delay time of a CCD delay line is generally determined by the relationship between the number of CCD stages and the clock cycle.
There is a relationship of ・・・・・・・・・・・・・・・0). Therefore, by adjusting the number of stages K of the CCD, this C
The delay time T of the CD delay line is T==4・n・τ (n
: natural number) (2), the delay time delayed by this CCD delay line will be a multiplication of the cycle of the subcarrier of the input reproduced color signal. Therefore, CCD
The reproduced color signal delayed by the delay line and the original reproduced color signal that is not delayed have the same subcarrier phase. Therefore, even if a video signal containing both of these reproduced color signals is switched and output according to the occurrence of skew, no discontinuity occurs in the subcarrier phase of the output signal.

Example An example of a specific embodiment of the present invention is shown in FIG.

In the figure, circuits given the same numbers as those in the conventional example of FIG. 2 are circuits having the same functions. For example, heads 1, 2, 3, switch 3A4 *SBs in both drawings,
5C11, reproduction luminance signal processing circuit 6, reproduction color signal processing circuit 7, output bassoph, -13, output terminal 14, terminal 15,
16. The gate circuits 12 each operate in the same way.

Therefore, since the operations of these circuits have been described previously, they will not be repeated here.

In FIG. 1, 18 is a crystal oscillator, which oscillates at a frequency four times the color signal subcarrier frequency. The output signal is then input as a clock to the CCD delay line 19 with a delay of 0.6H. At the same time, the output signal of the crystal oscillator 18 is μ
The frequency is divided by % by the frequency divider 20 and output as a color signal subcarrier frequency signal. The color signal subcarrier frequency signal output from the pure frequency divider 2o is input to the reproduced color signal processing circuit 7, and becomes a reference signal for the reproduced APC circuit. Therefore, the subcarrier phase of the reproduced color signal outputted from the reproduced color signal processing circuit is completely locked to the phase of the color signal subcarrier frequency signal outputted from the coarse frequency divider 2°. Furthermore, the subcarrier phase of this reproduced color signal is locked to the phase of the clock signal input to the CCD delay line 19.

Note that the reference signal of the conventional reproduction APC circuit was obtained from a unique internal crystal oscillator that oscillated at the color signal subcarrier frequency.

The CCD delay a19 receives a clock signal having a frequency four times the color signal subcarrier frequency, and also receives as an input signal a reproduced video signal having a subcarrier phase synchronized with the clock signal. Since the delay time T of this CCD delay line 19 is expressed as shown in the above equation (1), the number of stages K of this CCD delay line 19 is set to satisfy the above equation (2) = 4on・・・・・・・
...... (3), then the color signal subcarrier phase of the reproduced video signal delayed by this CCD delay line 19 and the undelayed original reproduced video signal output from the adder 8 is The phases are exactly the same, and even if the switch 5C11 is switched, discontinuity in the subcarrier phase will not occur.

The delay time T of this CCD delay 9 requires a delay time of o and sH, which is the amount of skew generated, and (3)
In order to satisfy the formula, the optimum number of stages is 456 stages. Note that the actual delay time of the CCD delay line is not exactly as shown in equation (1). This is a CCD
This is because the delay time of the delay line is determined in total, including not only the number of shift register stages in charge transfer but also the delay times in the charge injection stage and the output sample stage. However, since this charge injection stage and output sampling stage also operate according to the clock, if these are also considered as part of the number of delay stages of the CCD delay line, equation (1) is fully satisfied. Therefore, this meaning must be taken into consideration when setting K to 456 stages as described above.

In the present invention, no low-pass filter is provided after the CCD delay line 19. This is because the signal is also delayed by passing through the low-pass filter, so there is no point in managing the delay time to match the color signal subcarrier phase using the CCD delay line.However, this low-pass filter It also had the role of removing clock leakage from the output signal of the CCD delay line.In this regard, the leakage signal can be canceled by adding a signal with the opposite phase of the clock at the output stage of the CCD delay line.Alternatively, the leakage signal can be canceled by adding a signal with the opposite phase of the clock at the output stage of the CCD delay line. A low pass filter may be inserted between the output and the output buffer 13 to remove clock leakage signals.

In the present invention, the crystal oscillator 18 oscillates at a frequency four times the color signal subcarrier frequency, and this is used as a clock for the CCD delay line, and this signal is frequency-divided by μ to serve as a reference signal for the APC circuit for processing the reproduced color signal. It is said that In contrast, a crystal oscillator oscillates a signal at the color signal subcarrier frequency, which is used as a reference signal for the APC circuit, and this signal is multiplied by a PLL circuit to a four-times frequency signal.
It is conceivable to use a double frequency signal as the clock for the CCD delay line. This method can also be expected to have the same effects as the present invention. However, in reality, the output signal of the PLL circuit has a slight jitter due to electrical noise. Therefore, this electrical jitter causes the clock to fluctuate, causing an error in the delay time of the CCD delay line. As mentioned above, the delay time of the CCD delay line must be within an error of several nanoseconds.

This means that only an error of 10-4 is allowed. Therefore, it is extremely difficult to create a clock using a PLL circuit since the clock error must have an accuracy of 1o. In the present invention, since the clock is directly generated by a crystal oscillator, the above-mentioned clock accuracy can be ensured even if temperature characteristics, aging changes, etc. are taken into account.

As described in detail, the present invention is capable of performing skew correction in which almost no phase discontinuity of color signal subcarriers occurs under any environment or even when device variations are taken into account. Furthermore, the present invention can be implemented with a very simple and inexpensive configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional skew correction circuit.

Claims (1)

[Claims] In a circuit that corrects skew distortion that occurs during special playback of a VTR, a crystal oscillator that oscillates at a frequency four times the color signal subcarrier frequency and an output signal of the crystal oscillator that is
a frequency divider that divides the frequency by four; an automatic phase control circuit that controls the carrier wave phase of the reproduced color signal to be phase-locked to the output signal of the frequency divider; and a reproduced color signal that is the output of the automatic phase adjuster. and a reproduced luminance signal, an output signal from the crystal oscillator is used as a clock, a reproduced video signal output from the adder is used as an input signal, and the period of the clock is τ. at least a CCD delay line that delays and outputs an input signal by τ), and a switch circuit that selects and outputs the output signal of the adder and the output signal of the CCD delay line depending on the occurrence of skew. A VTR skew correction circuit characterized by being equipped with. (
n is a natural number)