JPS63146169A - Image memory - Google Patents

Abstract

PURPOSE:To increase a picture processing speed by preliminarily designating a window and automatically controlling the input/output of an image memory while always deciding whether a processing object picture element is placed within this window or not. CONSTITUTION:An address generating part 2 which designates coordinates in abscissa and ordinate directions of the processing object picture element, a recording circuit 7 which records the upper limit and the lower limit of a processing object picture area as coordinates in abscissa and ordinate directions, a comparing circuit 8 which compares the address and recorded coordinates with each other to perform decision, and a control circuit 9 which controls input/output of the image memory in accordance with the decision result are provided. The overall picture area of the processing object corresponding to the outside periphery of the processing object picture element is compared with the address of the processing object picture element to be accessed to decide whether the object picture element is placed within the window or not, thereby preliminarily automatically controlling input/output of the image memory. Thus, a complicated special pre-processing is unnecessary in a picture processing program when the window is handled in this program, and the picture processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image memory for storing and processing two-dimensional image data, and can be particularly used for image processing by a computer.

[Prior Art] Fig. 5 is a block diagram showing the configuration of a conventional image memory, Fig. 6 is a diagram showing the state of pixel allocation using conventional address signals, and Fig. 7 is a diagram showing the window area and object in the image area. Figure 8 is a flowchart showing the process of determining and processing the positional relationship between the target pixel and the window using a conventional image memory, and Figure 9 is a flowchart showing the pre-process of conventional image calculation processing. It is.

In FIG. 5, (1) is an address bus, (2) is an address generator that receives an address signal from the address bus (1) and generates the address of the pixel to be processed, and (3) is a unit that stores and processes image data. An image memory, (4) is a data bus, (5) is a control unit (hereinafter referred to as FCPUj) that controls the entire image memory mechanism, and (6) is a memory that stores control programs and the like.

Conventional image memory is structured as above,
When receiving an address signal from the address bus (1), the address generator (2) modifies the address, or when the address bus (1) and data bus (4) are shared, the address signal latching. The image data stored in the image memory (3) is
It is accessed by an address signal from an address generation section (2), and inputs and outputs data to and from a data bus (4). The entire image memory mechanism is controlled by the memory (6).
Processing is performed according to the image processing program within. In addition to the above programs, this memory (6) also contains
It also had an area for storing data other than images.

Next, this image processing operation will be explained.

The position of a pixel in the image memory (3) arranged in a matrix is determined by the image memory (3) in which the pixel is stored.
There is a one-to-one correspondence with the address in 3). For example, the sixth
When representing the position of a pixel indicated by hatching as shown in the figure, the content of the address signal is the coordinate in the horizontal direction of the pixel (hereinafter referred to as "X coordinate") in the lower part, and the coordinate in the vertical direction of the pixel in the upper part. coordinates (hereinafter referred to as "Y coordinates") are often assigned.

The address signal with such content is sent to the address generator (2).
) is output to the image memory (3), and the image memory (
3), a predetermined pixel is accessed and desired image processing is performed.

However, in actual image processing, a portion of the entire image area is sometimes cut out and image processing is performed within this area (hereinafter referred to as a "window"). Also, depending on the processing content, the pixel may be r3X3j or f5X5j
It was often treated as a small area (hereinafter referred to as a block) such as

For example, FIG. 7 shows the relationship between a window (hatched portion) in an image area and a target pixel when Ir3X3j block processing is performed. In this case, it is fine if the entire block is within the window, as at position A, but in some cases, a part of the block may protrude from the window, as at position B. In such a case, it is necessary to include in the image processing program a routine that detects whether some pixels within the block protrude from the window.

That is, as shown in the flowchart of FIG. 8, first, in step S1, an initial pixel P within a block is set. Then, in step S2, it is determined whether or not this initial pixel P is within the window. If it is outside the window, the reading of the initial pixel P is set to "0" in step S3, and calculation is performed in step S4.

On the other hand, if the initial pixel P is within the window, the calculation is performed directly in step S4. Next, in step S5, it is determined whether all the pixels in the block have been processed, and if there are unprocessed pixels, the initial pixel P is moved within the block in step S6, and then the process is performed again. The routine processing from step S2 is performed. The process continues until all the pixels in the block have been processed.

Further, as another means for detecting whether or not some pixels within a block protrude from the window, it is necessary to clear the peripheral area of the window in advance.

That is, as shown in the flowchart of FIG. 9, in step 311 pixels located above the window are cleared,
In step 312, pixels located below the window are cleared, further in step S13, pixels located to the left of the window are cleared, in step 814, pixels located to the right of the window are cleared, and then in step 515
This is used to perform arithmetic processing on pixels within a block.

[Problems to be Solved by the Invention] In the conventional image memory as described above, when performing image processing that treats pixels as blocks within a window, which is a specified area of a part of the entire image area, It was necessary to perform special processing as a countermeasure against the block of target pixels protruding from the target pixel.

That is, it is necessary to include a routine in the image processing program to detect whether some pixels within a block are outside the window, or to clear the area around the window in advance.

Therefore, it is extremely troublesome to create a program, and
Since the number of processing steps increases, there is a problem in that it also causes a reduction in processing speed.

Therefore, the present invention was made to solve this problem.A window is specified in advance, and the image is processed while constantly determining whether or not the pixel to be processed is located within this window. The purpose of this invention is to obtain an image memory that can automatically control memory input and output.

[Means for Solving the Problems] An image memory according to the present invention generates an address that specifies the horizontal and vertical coordinates of a pixel to be processed in an image memory that stores and processes two-dimensional image data. means for recording upper and lower limits of the image area to be processed as coordinates in the horizontal axis and vertical axis directions, respectively; The apparatus includes means for comparing and determining the recorded address with the recorded coordinates, and means for controlling input/output of the image memory based on the determination result.

[Operation] In this invention, the upper and lower limits of the image area to be processed, which correspond to the outer periphery of the window, are recorded in the recording means as coordinates in the horizontal axis and vertical axis directions, respectively, and these coordinates can be accessed. A comparator circuit compares the address from the address generator that specifies the horizontal and vertical coordinates of the pixel to be processed, and determines whether the pixel to be processed is located inside the window. Memory input/output can be automatically controlled in advance.

[Embodiment] Fig. 1 is a block diagram showing the configuration of an image memory according to an embodiment of the present invention, Fig. 2 is a diagram showing the state of pixel allocation according to address signals in an embodiment of the invention, The figure shows a state in which a window area is designated within an image area according to an embodiment of the present invention, and FIG. 4 is a diagram showing a case where a target pixel is located outside the designated window area. In addition, in the figure, (1) to (6) are the same or corresponding components to the components of the above-mentioned conventional example.

In FIG. 1, (7) is a recording circuit that records the upper and lower limits of the window, which is the image area to be processed, as X-Y coordinates in the horizontal and vertical axes.
) are the Y coordinate recording section (7a) and X coordinate recording section (7b) of the window upper limit, and the Y coordinate recording section (7b) of the window lower limit.
C) and an X coordinate recording section (7d). (8
) compares the X-Y coordinates in the horizontal and vertical directions of the pixel to be processed generated from the address generation unit (2) and the X-Y coordinates of the upper and lower limits of the window to be processed in the recording circuit (7), respectively. This comparison circuit (8) is a comparator (8a) between the Y coordinate of the target pixel and the Y coordinate of the upper limit of the window.
and a comparator (8b) between the X coordinate of the target pixel and the X coordinate of the window upper limit, a comparator (8G) between the Y coordinate of the target pixel and the Y coordinate of the window lower limit, and a comparator (8G) between the X coordinate of the target pixel and the X coordinate of the window lower limit. It consists of a comparator (8d) with the coordinates. (9) is a control circuit that determines the comparison result of the comparison circuit (8) and controls the input/output of the image memory (3), and is composed of a determiner (9a) and a buffer (9b).

In the image memory of this embodiment configured as described above, the one-to-one correspondence between the position of a pixel on the image, that is, its X-Y coordinates, and the address on the image memory is basically Same as before. However, as shown in Figure 2, both the X and Y coordinates have one more bit added above the bits necessary to access the entire image memory (hereinafter referred to as the "entire image area"). , constitutes an address signal. This is done when the size of the window, which will be described later, matches the entire image area, and actually the image memory (3)
The address signal input to is obtained by removing the additional bits of the X and Y coordinates from the address configured as described above.

The image processing operation by the image memory of this embodiment will be explained below.

When processing the hatched window area in Fig. 3, first pixel P1 (×1
．． yl), the lower right pixel P2 (x2゜'i/2 > specifies the window. The CPU (5) uses the address bus (1
) with the additional bit set to “0゛′” Pixel Pi (Xl,
yl > address signal, and the upper (Y coordinate) and lower (X coordinate) thereof are respectively stored in the Y coordinate recording section (7a) of the window upper limit and the X coordinate recording section (7b) of the window upper limit.
latch on.

Next, similarly, the pixel P2 (X2, V2) is latched to the Y coordinate recording section (7C) at the lower limit of the window and the X coordinate recording section (7d) at the lower limit of the window, respectively.

These four latched coordinates, yl, ×1, y2,
x2 becomes an input to one of the comparators (8a) and (8b) between the target pixel and the window upper limit, and the comparators (8G) and (8d) between the target pixel and the window lower limit, respectively, of the comparison circuit (8).

With the above operations, when accessing the image memory (3) after defining the window, CPtJ (5) transfers the address signal of any pixel P (X, /) to the address bus (1
), the address is input to the address generator (2), the address is latched or modified as necessary by the address generator (2), the additional bits are removed, and the address is input to the image memory (3). output as an address.

At this time, the address signal is simultaneously divided into upper (Y coordinate) and lower (X coordinate) with additional bits, and the Y coordinate is determined by the comparators (8a) and (8) between the target pixel and the window upper limit.
In b), the X coordinate is input to the comparator (8c) and (8d>) between the target pixel and the lower limit of the window, respectively. Comparison circuit (8)
Now, compare these inputs with the input from the recording circuit (7), and when yl>'/, Xi >X, V2 <7% In case °“Op
Output t. The determiner (9a) of the control circuit (9) is composed of these four comparison circuits (8a).

Take the logical sum of the outputs of (8b), (8c), and (8d>,
The result is used as a chip select input of the image memory (3) and an enable signal of the buffer (9b). Here, if the logical sum is "0", four comparison circuits (8
The outputs of a>, (8b), (8c), and (8d> are all “0”
This is limited to the case where x1≦X≦×2 and y1≦y≦y2 hold simultaneously.

This means that the accessed pixel is located within the window area.

Therefore, at this time, the image memory (3) is chip-selected (C3="O"), and writing and reading from the memory is possible.

On the other hand, if the logical sum is “1'', then X<Xl,
2 <X, y<yl, V2 <V, at least 1
This is the case when the following is true.

This means that the accessed pixel is located outside the window area.

Therefore, at this time, the image memory (3) is not chip-selected (C3="1") and the buffer? (9
t)) is enabled and the value “On” is the data bus (4
). That is, writing to the image memory becomes impossible, and reading becomes Ore.

The above is the operation when accessing the image memory according to this embodiment.

Here, we will further explain that the address signal is constructed by adding one bit at a time to the upper bits necessary to access the entire image area for both the X and Y coordinates, as shown in Figure 2. do.

In fact, when the pixel to be accessed is outside the window, this can occur if the target pixel is near the border inside the window and the pixel is moved relatively from there.

FIG. 4 shows an example in which a part of the block protrudes outside the top of the window when a block of I''3×3Jl is constructed around the target pixel AO on the upper side of the designated window area.

If the window size matches the entire image area (in the Y direction in this case), as in this example, the Y
If there is no additional bit in the address, the pixel A1 that protrudes from the window will actually be positioned at A2, and will be determined to be a pixel inside the window, resulting in pixel A2 being accessed. However, if additional bits are provided for the X and Y addresses, a virtual memory space four times larger than the real memory space will be accessed, as shown in Figure 4.
In the above example, the pixel A1 that protrudes above the window is positioned at the bottom edge A3 in the virtual memory space, and is correctly determined as a pixel outside the window.

The above example rarely concerns the top edge of the window, but the same applies to other edges, such as the X address, Y address, etc.
By configuring the virtual memory space by providing additional bits in the address, pixels outside the window can be prevented from being located substantially inside the window.

Through the above operations, in this embodiment, memory access is possible for pixels inside the window, regardless of how the window is set within the entire image area.
Pixels outside the window cannot be automatically written to and read as "0". In this way, the means for controlling the input/output of the image memory (3) based on the determination result is as follows:
Control such as regulating the input/output of the image memory (3) can be performed depending on the usage.

[Effects of the Invention] As explained above, the image memory of the present invention includes an addressing means for specifying the horizontal and vertical coordinates of the pixel to be processed, and a means for specifying the upper and lower limits of the image area to be processed on the horizontal and vertical axes. Since it has means for recording each coordinate in the vertical axis direction, means for comparing and determining the address and the recorded coordinate, and means for controlling the input/output of the image memory based on the determination result, the window By comparing the entire image area to be processed corresponding to the outer periphery with the address of the pixel to be processed to be accessed and determining whether the target pixel is located inside the window, input/output of the image memory can be performed in advance. Since it can be controlled automatically, when handling windows in an image processing program, there is no need to perform complicated special preprocessing in the program, and the processing steps for that can be omitted, so the image processing speed can be increased. It is possible to improve the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image memory according to an embodiment of the present invention, FIG. 2 is a diagram showing the state of pixel allocation according to an address signal according to an embodiment of the present invention, and FIG. 3 is a diagram showing the state of pixel allocation according to an embodiment of the present invention. A diagram showing a state in which a window area is specified within an image area in one embodiment, FIG. 4 is a diagram showing a case where a target pixel is located outside the specified window area, and FIG. 5 is a diagram showing the configuration of a conventional image memory. Fig. 6 is a block diagram showing the state of pixel allocation using conventional address signals;
The figure shows the relationship between the window area in the image area and the target pixel, Figure 8 is a flowchart showing the process of determining and processing the positional relationship between the target pixel and the window using a conventional image memory, and Figure 9 is the conventional image memory. This is a flowchart A showing the pre-processing of the image @ calculation process. In the figure, 1 near address bus, 2 near address generation section, 3: image memory, 5: control section (CPU), 6: memory, 7: recording circuit, 8: comparison circuit,
9: Control a circuit, 9a: Determiner, 9b: Buffer 1. In addition, in the figures, the same reference numerals and the same symbols indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] An image memory for storing and processing image data, comprising: addressing means for specifying the coordinates of a pixel to be processed along the horizontal and vertical axes; An image characterized by comprising means for recording each as a coordinate in the vertical axis direction, means for comparing and determining the address and the recorded coordinate, and means for controlling input/output of the image memory based on the determination result. memory.