JPS63144740U - - Google Patents
Info
- Publication number
- JPS63144740U JPS63144740U JP3600087U JP3600087U JPS63144740U JP S63144740 U JPS63144740 U JP S63144740U JP 3600087 U JP3600087 U JP 3600087U JP 3600087 U JP3600087 U JP 3600087U JP S63144740 U JPS63144740 U JP S63144740U
- Authority
- JP
- Japan
- Prior art keywords
- inverting input
- input terminal
- output terminal
- terminal
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図は本考案によるＦＳＫ変調回路の一実施
例を表わす回路図、第２図は従来のＦＳＫ変調回
路を表わす回路図、第３図はマルチ・バイブレー
タ回路を表わす回路図である。
１…演算増幅器、２…反転入力端子、３…非反
転入力端子、４…出力端子、５，７…抵抗、６…
コンデンサ、９…ゲート、１２…データ入力端子
、１５，１６…可変抵抗、１７…周波数切替回路
。
FIG. 1 is a circuit diagram showing an embodiment of the FSK modulation circuit according to the present invention, FIG. 2 is a circuit diagram showing a conventional FSK modulation circuit, and FIG. 3 is a circuit diagram showing a multi-vibrator circuit. 1... Operational amplifier, 2... Inverting input terminal, 3... Non-inverting input terminal, 4... Output terminal, 5, 7... Resistor, 6...
Capacitor, 9... Gate, 12... Data input terminal, 15, 16... Variable resistor, 17... Frequency switching circuit.
Claims (1)
有する演算増幅器と、前記反転入力端子と前記出
力端子間を接続する第１の抵抗と、前記反転入力
端子と接地間を接続するコンデンサと、前記非反
転入力端子と前記出力端子間に接続する第２の抵
抗と、前記非反転入力端子と接地間を接続する第
１の可変抵抗と、オープンコレクタ出力端子を有
するゲートと、このゲートの出力端子側に一端が
接続され他端が前記非反転入力端子に接続される
第２の可変抵抗とから構成されるＦＳＫ変調回路
。 an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal; a first resistor connecting the inverting input terminal and the output terminal; a capacitor connecting the inverting input terminal and ground; a second resistor connected between the non-inverting input terminal and the output terminal; a first variable resistor connecting the non-inverting input terminal and ground; a gate having an open collector output terminal; and an output terminal of the gate. and a second variable resistor having one end connected to the side and the other end connected to the non-inverting input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3600087U JPS63144740U (en) | 1987-03-13 | 1987-03-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3600087U JPS63144740U (en) | 1987-03-13 | 1987-03-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63144740U true JPS63144740U (en) | 1988-09-22 |
Family
ID=30846005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3600087U Pending JPS63144740U (en) | 1987-03-13 | 1987-03-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63144740U (en) |
-
1987
- 1987-03-13 JP JP3600087U patent/JPS63144740U/ja active Pending
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