JPS63143836A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS63143836A JPS63143836A JP61290406A JP29040686A JPS63143836A JP S63143836 A JPS63143836 A JP S63143836A JP 61290406 A JP61290406 A JP 61290406A JP 29040686 A JP29040686 A JP 29040686A JP S63143836 A JPS63143836 A JP S63143836A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- power supply
- semiconductor chip
- semiconductor device
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特に、半導体チップの表面を樹
脂封止してなる半導体装置に適用して有効な技術に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a semiconductor device, and particularly to a semiconductor device in which the surface of a semiconductor chip is sealed with resin.
ＤＩＬＰ、ＬＣＣ等の樹脂封止型半導体装置の半導体チ
ップの周辺部には、ｆｌｔｌ起源が延在している。１ｔ
！源配線は、基準電圧用配線及び電源電圧用配線で構成
されている。基準電圧用配線は例えば回路の接地電位Ｖ
ｓ ｓ （Ｏ［Ｖ］ ）、 ｆ！を源電圧用配線は例
えば回路の動作電圧Ｖ ｃ ｃ （５［Ｖ］ ）を夫々
印加している。The fltl origin extends to the periphery of the semiconductor chip of a resin-sealed semiconductor device such as a DILP or LCC. 1t
! The source wiring includes a reference voltage wiring and a power supply voltage wiring. The reference voltage wiring is, for example, the ground potential V of the circuit.
s s (O[V] ), f! For example, the circuit operating voltage Vcc (5 [V]) is applied to each of the source voltage wirings.
電源配線は、アルミニウム膜等の低抵抗値の導電層を用
い、５０〜１００［μｍ］程度の比較的太い配線幅で構
成されている。つまり、電源配線は。The power supply wiring uses a conductive layer having a low resistance value such as an aluminum film, and has a relatively wide wiring width of about 50 to 100 [μm]. In other words, the power wiring.
外部出力段回路の動作等で生じる電位変動（ノイズ）を
低減し１回路の誤動作を防止できるように。Reduces potential fluctuations (noise) caused by the operation of external output stage circuits and prevents malfunction of one circuit.
所定の配線容量を有するように構成されている。It is configured to have a predetermined wiring capacity.
この種の半導体装置は、前記電源配線上を含む半導体チ
ップ上にパッシベーション膜を設け、その全体を樹脂封
止（レジンモールド）している。樹脂封圧は、樹脂の収
縮による応力がパッシベーション膜に加わり、下地に柔
かいアルミニウム膜が存在する部分のパッシベーション
膜にクラックを生じ易い、このクラックは、面積が大き
な前記電源配線の夫々のうち、特に、半導体チップの角
部分に延在する電源配線部分のパッシベーション膜に生
じ易い、パッシベーション膜のクラックの発生は、耐湿
性を劣化させ、電源配ＩＩ（アルミニウムａ）を腐蝕さ
せる。In this type of semiconductor device, a passivation film is provided on the semiconductor chip including the power supply wiring, and the whole is sealed with resin (resin mold). Resin sealing pressure is such that stress due to resin contraction is applied to the passivation film, which tends to cause cracks in the passivation film in areas where there is a soft aluminum film underneath. Cracks in the passivation film, which are likely to occur in the passivation film of the power wiring portion extending to the corners of the semiconductor chip, deteriorate the moisture resistance and corrode the power wiring II (aluminum a).
また、前述の半導体チップの角部分のパッシベーション
膜に加わる応力は、前記電源配線の位置をその下地絶縁
膜との接着力に抗して変動させる。Further, the stress applied to the passivation film at the corner portion of the semiconductor chip described above causes the position of the power supply wiring to change against the adhesive force with the underlying insulating film.
この電源配線の変動は、配線自信のＭ１傷、破壊を生じ
るばかりでなく、電源配線下に存在する絶縁膜や半導体
素子の損傷、破壊を生じさせ、電気的信頼性を低下させ
る。This variation in the power supply wiring not only causes M1 scratches and destruction of the wiring itself, but also damages and destruction of the insulating film and semiconductor elements existing under the power supply wiring, reducing electrical reliability.
そこで、樹脂の収縮による応力が最大に加わる部分、特
に、半導体チップの角部分の電源配線に。Therefore, the power supply wiring is used in areas where the stress due to resin contraction is the greatest, especially at the corners of semiconductor chips.
配線幅寸法を複数に分割するスリットを設ける技術を適
用することが考えられる。スリットは、電源配線の配線
長方向に延在する。、１１！＆い形状で構成される。こ
の技術を適用すると、電源配線及びその上のパッシベー
ション膜に加わる応力を分散させることができる。つま
り、前述のパッシベーション膜のクラックの発生、電源
配線の損傷、破壊、電源配線下の絶縁膜や半導体１子の
損傷、破壊を防止することができる。It is conceivable to apply a technique of providing slits that divide the wiring width dimension into a plurality of parts. The slit extends in the wiring length direction of the power supply wiring. , 11! It is composed of a large shape. By applying this technique, stress applied to the power supply wiring and the passivation film thereon can be dispersed. In other words, it is possible to prevent the above-mentioned cracks in the passivation film, damage and destruction of the power supply wiring, and damage and destruction of the insulating film and semiconductor single layer under the power supply wiring.
なお、半導体チップの角部分の配線にスリットが設けら
れた半導体装置については１例えば、特開昭５７−４５
２５９号公報に記載されている。Regarding semiconductor devices in which slits are provided in the wiring at the corner portions of semiconductor chips, for example, Japanese Patent Laid-Open No. 57-45
It is described in Publication No. 259.
しかしながら、本発明者は、前記樹脂封止型半導体装置
における検討の結果１次の問題点が生じることを見出し
た。つまり、スリットの占有面積を加算した分、前記電
源配線の占有面積が著しく増加するために、半導体チッ
プの集積度が低下する。However, as a result of studies on the resin-sealed semiconductor device, the present inventor found that the first problem occurred. In other words, since the area occupied by the power supply wiring increases significantly by adding the area occupied by the slit, the degree of integration of the semiconductor chip decreases.
本発明の目的は、樹脂封止型半導体装置の半導体チップ
の電気的信頼性を向上すると共に、半導体チップの集積
度を向上することが可能な技術を提供することにある。An object of the present invention is to provide a technique that can improve the electrical reliability of a semiconductor chip of a resin-sealed semiconductor device and improve the degree of integration of the semiconductor chip.
本発明の他の目的は、樹脂封止に起因する半導体チップ
のパッシベーション膜のクラック等を防止することが可
能な技術を提供することにある。Another object of the present invention is to provide a technique that can prevent cracks in the passivation film of a semiconductor chip caused by resin sealing.
本発明の他の目的は、半導体チップの周辺部に延在する
電源配線の配線容量を充分に確保し、電源配線の占有面
積を縮小することが可能な技術を提供することにある。Another object of the present invention is to provide a technique capable of ensuring a sufficient wiring capacity of power supply wiring extending around the periphery of a semiconductor chip and reducing the area occupied by the power supply wiring.
本発明の前記ならびにその他の目的と新規な特徴は１本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち１代表的なものの概
要を説明すれば、下記のとおりである。An overview of one typical invention disclosed in this application is as follows.
樹脂封止型半導体装置において、半導体チップの周辺部
に延在する電源配線に、配線幅寸法を複数に分割する穴
部を設け、該穴部を前記電源配線の配線長方向に所定間
隔で複数設ける。In a resin-sealed semiconductor device, a power supply wiring extending around the periphery of a semiconductor chip is provided with a hole that divides the width of the wiring into a plurality of parts, and a plurality of holes are formed at predetermined intervals in the length direction of the power supply wiring. establish.
上記した手段によれば、前記電源配線及びその上のパッ
ジベージ１ン膜に加わる応力を分散して低減できるので
、パッジベージ運ン膜のクラックの発生、電源配線の損
傷、破壊或は電源配線下の絶縁膜や半導体素子の損傷、
破壊を防止すると共に、前記配線長方向の穴部間に存在
する電源配線で配線容量を増加できるので、電源配線の
占有面積を縮小することができる。According to the above-mentioned means, the stress applied to the power supply wiring and the pudge page film thereon can be dispersed and reduced, thereby preventing cracks in the pudge page transport film, damage or destruction of the power supply wiring, or damage to the power supply wiring under the power supply wiring. Damage to insulating films and semiconductor elements,
In addition to preventing damage, the wiring capacity can be increased by the power wiring existing between the holes in the wiring length direction, so that the area occupied by the power wiring can be reduced.
以下、本発明の構成について１本発明をＤＩＬＰ方式の
樹脂封止型半導体装置に適用した一実施例とともに説明
する。Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to a DILP type resin-sealed semiconductor device.
なお、企図において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In addition, in the plan, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
（実施例〕
本発明の一実施例であるＤＩＬＰ方式の樹脂封止型半導
体装置の概略構成を第１図（断面図）で示す。(Example) FIG. 1 (cross-sectional view) shows a schematic configuration of a DILP type resin-sealed semiconductor device which is an example of the present invention.
第１図に示すように、４！１脂封止型半導体装置は、タ
ブ部ＩＡに塔載された半導体チップ２．リードｌのイン
ナーリード部１１３の夫々を樹脂封止部４で封止して構
成されている。リード１のアウターリード部ＩＣは、樹
脂封止部４から突出するように構成されている。As shown in FIG. 1, the 4!1 fat-sealed semiconductor device includes two semiconductor chips mounted on a tab portion IA. Each of the inner lead portions 113 of the lead 1 is sealed with a resin sealing portion 4. The outer lead portion IC of the lead 1 is configured to protrude from the resin sealing portion 4.
半導体チップ２は、第２図（要部拡大断面図）で示すよ
うに、単結晶シリコンからなるＰ−型半導体基板２Ａの
主面に、ＭＯ８ＦＥＴＱ等の半導体素子が設けられてい
る。半導体素子は、フィールド絶縁膜２Ｂ及びｐ型チャ
ネルストッパ領域２Ｃでその領域が規定され、他の領域
と電気的に分離されている。ＭＯ３ＦＥＴＱは、半導体
基板２人、ゲート絶縁膜２Ｄ、ゲート電極２Ｅ、ソース
領域又はドレイン領域として使用されるｎ０型半導体領
域２Ｆで構成されている。As shown in FIG. 2 (an enlarged cross-sectional view of main parts), the semiconductor chip 2 includes semiconductor elements such as MO8FETQ provided on the main surface of a P-type semiconductor substrate 2A made of single crystal silicon. A region of the semiconductor element is defined by a field insulating film 2B and a p-type channel stopper region 2C, and is electrically isolated from other regions. MO3FETQ is composed of two semiconductor substrates, a gate insulating film 2D, a gate electrode 2E, and an n0 type semiconductor region 2F used as a source region or a drain region.
前記ＭＯ５ＦＥＴＱのｔ型半導体領域２Ｆには、第１層
目配線２Ｉが接続されている。配線２Ｉは、層間絶縁膜
２Ｇに形成された接続孔２Ｈを通してれ４型半導体領域
２Ｆに接続されている。配線２１は１例えば、比抵抗値
が小さいアルミニウム膜。A first layer wiring 2I is connected to the t-type semiconductor region 2F of the MO5FETQ. The wiring 2I is connected to the type 4 semiconductor region 2F through a connection hole 2H formed in the interlayer insulating film 2G. The wiring 21 is made of, for example, an aluminum film with a small specific resistance value.
所定の添加物（Ｓｉ、Ｃｕ）が含有されたアルミニウム
膜で形成されている。It is formed of an aluminum film containing predetermined additives (Si, Cu).
配線２■の上部には、眉間絶縁膜２Ｊを介在させて第２
層口配線２Ｌが設けられている。配線２Ｌは、眉間絶縁
膜２Ｊに形成される接続孔２Ｋを通して配線２Ｉや、直
接、半導体領域２Ｆに接続されている。配線２Ｌは、信
号配線として使用される以外に、半導体チップ２の周辺
部において。A second glabellar insulating film 2J is interposed on the upper part of the wiring 2■.
A layer opening wiring 2L is provided. The wiring 2L is connected to the wiring 2I or directly to the semiconductor region 2F through a connection hole 2K formed in the glabellar insulating film 2J. The wiring 2L is used not only as a signal wiring but also in the periphery of the semiconductor chip 2.
外部端子（ポンディングパッド）Ｂｒ’、電源配線とし
て使用されている。電源配線は、第２図及び第３図（要
部拡大平面図）に示すように、半導体チップ２の各々の
辺に沿って延在するように構成されている。第２図及び
第３図において、電源配線は、基準電圧用配線Ｖ８１１
Ｌ／か図示していないが、実際には、基準電圧用配線Ｖ
ｓ ｓと電源電圧用配線Ｖｃｃとを一組として延在さ
せている。通常、電源配線は、入力段又は出力段回路（
入力又は出カバソファ回路）の上部を延在するように構
成されている。配線２Ｌは、前記配線２Ｉと同様に、低
抵抗値のアルミニウム膜等で形成する。External terminal (ponding pad) Br' is used as power supply wiring. The power supply wiring is configured to extend along each side of the semiconductor chip 2, as shown in FIGS. 2 and 3 (enlarged plan views of main parts). In Figures 2 and 3, the power supply wiring is the reference voltage wiring V811.
Although not shown in the diagram, the reference voltage wiring V
ss and the power supply voltage wiring Vcc are extended as a set. Normally, power supply wiring is connected to the input stage or output stage circuit (
(input or output cover circuit). The wiring 2L is formed of a low resistance aluminum film or the like, similarly to the wiring 2I.
前記配＄２Ｌ上を含む半導体チップ２の全面には、保護
膜としてのパッシベーション膜２Ｍが設けられている。A passivation film 2M as a protective film is provided on the entire surface of the semiconductor chip 2 including the top of the wiring 2L.
パッシベーション膜２Ｍは１例えば、耐湿性に優れたプ
ラズマ窒化シリコン膜で形成されている。The passivation film 2M is formed of, for example, a plasma silicon nitride film having excellent moisture resistance.
前記半導体チップ２の外部端子ＢＰとして使用される配
線２Ｌには、ボンディングワイヤ３の一端が接続されて
いる。ボンディングワイヤ３の他端は、インナーリード
部ＩＢに接続されている。One end of a bonding wire 3 is connected to a wiring 2L used as an external terminal BP of the semiconductor chip 2. The other end of the bonding wire 3 is connected to the inner lead portion IB.
外部端子ＢＰとボンディングワイヤ３との接続は。The connection between external terminal BP and bonding wire 3 is as follows.
パッシベーション膜２Ｍに形成された開口部２Ｎを通し
て行われる。This is performed through an opening 2N formed in the passivation film 2M.
前述の樹脂封止部（レジンモールド部）４は、半導体チ
ップ２（実際にはパッジページ１ン膜２Ｍ上）を覆うよ
うに構成されている。The resin sealing part (resin mold part) 4 described above is configured to cover the semiconductor chip 2 (actually on the pad page 1 film 2M).
このように構成される樹脂封止型半導体装置において、
第３図において、半導体チップ２の周辺部に延在する前
記電源配線（Ｖｓｓ、２Ｌ）には。In the resin-sealed semiconductor device configured in this way,
In FIG. 3, the power supply wiring (Vss, 2L) extending around the periphery of the semiconductor chip 2 includes:
配線幅寸法を複数に分割すると共に、電源配線（２Ｌ）
の配線長方向に所定間隔で複数設けられた穴部２ｍが構
成されている。詳述すれば、穴部２ａは、半導体チップ
２の中心点Ｐがら放射状に引き出された応力の作用線（
Ｌ）上における電源配線（２Ｌ）の配線幅方向を複数に
分割するように構成されている。前記中心点Ｐは、半導
体チップ２と樹脂封止部４との熱膨張率差で生じる応力
、つまり樹脂の収縮で生じる応力が実質的に作用しない
点（各方向から作用する応力が打ち消し合う点）である
、穴部２ｊ１は１分割された電源配線（２Ｌ）の配線幅
寸法ｊｌｔ−Ω５の夫々が、充分に応力を分散できる所
定値を越えない位置に設けられている。配線幅方向の穴
部２Ｑの数は、充分に応力を分散できるように、ｌ又は
複数で形成する。配線長方向に配置される穴部２Ｑの間
隔は、同様に。In addition to dividing the wiring width into multiple parts, the power wiring (2L)
A plurality of holes 2m are provided at predetermined intervals in the wiring length direction. To be more specific, the hole 2a is located along the line of action (
The power supply wiring (2L) on L) is configured to be divided into a plurality of parts in the wiring width direction. The center point P is a point where the stress caused by the difference in coefficient of thermal expansion between the semiconductor chip 2 and the resin sealing part 4, that is, the stress caused by the contraction of the resin, does not substantially act (the point where the stresses acting from each direction cancel each other out). ), the hole portion 2j1 is provided at a position where the wiring width dimension jlt-Ω5 of each divided power supply wiring (2L) does not exceed a predetermined value that can sufficiently disperse stress. The number of holes 2Q in the wiring width direction is set to l or a plurality of holes so that stress can be sufficiently dispersed. The intervals between the holes 2Q arranged in the wiring length direction are the same.
充分に応力を分散できる所定寸法を越えないように設定
する。Set the dimensions so that they do not exceed a predetermined size that can sufficiently disperse stress.
穴部２Ｑの関口形状（上面から見た形状）は１円形状で
形成する。また、穴部２ａの開口形状は。The Sekiguchi shape (the shape seen from the top) of the hole 2Q is formed into a circular shape. Moreover, the opening shape of the hole portion 2a is as follows.
楕円形状、方形状で形成してもよい。It may be formed in an elliptical or rectangular shape.
穴部２Ωは１通し穴（貫通穴）で形成する。つまり、通
し穴で形成される穴部２Ｑは、マスクパターン（フォト
レジストマスクパターン）を変更するだけで、電源配置
１２Ｌと同一工程で簡単に形成することができる。また
、穴部２Ｑは、プロセス的に霞しくなるが、止め穴で形
成してもよい。The hole portion 2Ω is formed by one through hole (through hole). In other words, the hole portion 2Q formed by the through hole can be easily formed in the same process as the power source arrangement 12L by simply changing the mask pattern (photoresist mask pattern). Further, the hole portion 2Q may be formed by a stopper hole, although the hole portion 2Q becomes hazy due to the process.
前記穴部２ｇは、少なくとも、ｔＳ脂の収縮による応力
が最つも大きな半導体チップ２の角部に設ければよい。The hole 2g may be provided at least at the corner of the semiconductor chip 2 where stress due to contraction of the tS fat is greatest.
このように、前記穴部２Ｑを設けることにより。By providing the hole 2Q in this manner.
前記電源配線（２Ｌ）及びその上のパッシベーション膜
２Ｍに加わる応力を分散して低減できるので、パッシベ
ーション膜２Ｍのクラックの発生、電源配、１（２Ｌ）
の損傷、破壊或は電源配線（２Ｌ）下の眉間絶縁＠２Ｊ
や半導体素子の損傷、破壊を防止する二とができる。こ
れと共に、配線長方向における穴部２Ｑ間に電源配線（
２Ｌ）を存在させ、配線容量を増加することができるの
で、電源配線（２Ｌ）の占有面積を縮小することができ
る。したがって、樹脂封止型半導体装置の半導体チップ
２の電気的信頼性を向上することができると共に。Since the stress applied to the power supply wiring (2L) and the passivation film 2M thereon can be dispersed and reduced, cracks in the passivation film 2M and power supply wiring 1 (2L) can be reduced.
Damage, destruction or insulation between the eyebrows under the power supply wiring (2L) @2J
It is also possible to prevent damage and destruction of semiconductor elements. Along with this, the power supply wiring (
2L) and increase the wiring capacity, the area occupied by the power supply wiring (2L) can be reduced. Therefore, the electrical reliability of the semiconductor chip 2 of the resin-sealed semiconductor device can be improved.
半導体チップ２の集積度を向上することができる。The degree of integration of the semiconductor chip 2 can be improved.
以上１本発明者によってなされた発明を、前記実施例に
基づき具体的に説明したが１本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて１種々変形し得ることは勿論である。Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and may be modified in various ways without departing from the gist thereof. Of course.
例えば１本発明は、樹脂の収縮による応力を充分に分散
できるように、電源配線に穴部をランダムに配置しても
よい。For example, in one aspect of the present invention, holes may be randomly arranged in the power supply wiring so that stress due to resin contraction can be sufficiently dispersed.
また９本発明は、半導体チップの周辺部に延在する電源
配線に限らず、半導体チップの周辺部に存在する配線（
例えば信号用アルミニウム配線）に適用することができ
る。Furthermore, the present invention is not limited to power supply wiring extending around the periphery of a semiconductor chip, but also includes wiring existing at the periphery of a semiconductor chip (
For example, it can be applied to signal aluminum wiring).
（発明の効果）
本願において開示される発明のうち１代表的なものによ
って得ることができる効果を簡単に説明すれば１次のと
おりである。(Effects of the Invention) The following is a brief explanation of the effects that can be obtained by one typical invention among the inventions disclosed in this application.
樹脂封止型半導体装置において、半導体チップの電気的
信頼性を向上すると共に、半導体チップの集積度を向上
することができる。In a resin-sealed semiconductor device, the electrical reliability of the semiconductor chip can be improved and the degree of integration of the semiconductor chip can be improved.
第１図は、本発明の一実施例である樹脂封止型半導体装
置の概略構成を示す断面図、
第２図は、第１図に示す樹脂封止型半導体装置の要部拡
大断面図。
第３図は、第１図に示す樹脂封止型半導体装置の要部拡
大平面図である。
図中、ｌ・・・リード、ｌＢ・・・インナーリード部、
２・・・半導体チップ、２Ｉ、２Ｌ・・・配線、２Ｑ・
・・穴部、３・・・ボンディングワイヤ、４・・・樹脂
封止部、ＢＰ・・・外部端子、Ｖｓｓ、Ｖｃｃ・・・電
源配線である。
第 ３ 図FIG. 1 is a sectional view showing a schematic configuration of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of a main part of the resin-sealed semiconductor device shown in FIG. 1. FIG. 3 is an enlarged plan view of essential parts of the resin-sealed semiconductor device shown in FIG. 1. In the figure, l...lead, lB...inner lead part,
2...Semiconductor chip, 2I, 2L...Wiring, 2Q.
... Hole portion, 3... Bonding wire, 4... Resin sealing portion, BP... External terminal, Vss, Vcc... Power supply wiring. Figure 3
Claims (1)
ーション膜を設け、この半導体チップ表面を樹脂封止し
てなる半導体装置であって、前記配線に配線幅寸法を複
数に分割する穴部を設け、該穴部を前記配線の配線長方
向に所定間隔で複数設けたことを特徴とする半導体装置
。 ２、前記穴部は、通し穴或は止め穴で形成されているこ
とを特徴とする特許請求の範囲第１項に記載の半導体装
置。 ３、前記穴部の開口形状は、円形状、楕円形状又は方形
状で構成されていることを特徴とする特許請求の範囲第
１項又は第２項に記載の半導体装置。 ４、前記穴部は、少なくとも前記半導体チップの角部分
に延在する電源配線に設けられていることを特徴とする
特許請求の範囲第１項乃至第３項に記載の夫々の半導体
装置。[Scope of Claims] 1. A semiconductor device in which a passivation film is provided on wiring extending to the periphery of a semiconductor chip, and the surface of the semiconductor chip is sealed with resin, the wiring having a plurality of wiring width dimensions. 1. A semiconductor device characterized in that a plurality of holes are provided at predetermined intervals in the wiring length direction of the wiring. 2. The semiconductor device according to claim 1, wherein the hole is formed as a through hole or a stopper hole. 3. The semiconductor device according to claim 1 or 2, wherein the opening shape of the hole is circular, elliptical, or rectangular. 4. The semiconductor device according to any one of claims 1 to 3, wherein the hole is provided in a power supply wiring extending at least to a corner portion of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61290406A JPS63143836A (en) | 1986-12-08 | 1986-12-08 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61290406A JPS63143836A (en) | 1986-12-08 | 1986-12-08 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63143836A true JPS63143836A (en) | 1988-06-16 |
Family
ID=17755600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61290406A Pending JPS63143836A (en) | 1986-12-08 | 1986-12-08 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63143836A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322535A (en) * | 1989-06-20 | 1991-01-30 | Oki Electric Ind Co Ltd | Resin sealed semiconductor device |
| JP2000349165A (en) * | 1999-03-25 | 2000-12-15 | Seiko Instruments Inc | Semiconductor integrated circuit device and manufacture thereof |
-
1986
- 1986-12-08 JP JP61290406A patent/JPS63143836A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322535A (en) * | 1989-06-20 | 1991-01-30 | Oki Electric Ind Co Ltd | Resin sealed semiconductor device |
| JP2000349165A (en) * | 1999-03-25 | 2000-12-15 | Seiko Instruments Inc | Semiconductor integrated circuit device and manufacture thereof |
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