JPS63142812A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63142812A JPS63142812A JP29108686A JP29108686A JPS63142812A JP S63142812 A JPS63142812 A JP S63142812A JP 29108686 A JP29108686 A JP 29108686A JP 29108686 A JP29108686 A JP 29108686A JP S63142812 A JPS63142812 A JP S63142812A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- molecular beam
- type
- film
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 9
- 230000000873 masking effect Effects 0.000 claims 1
- 238000001451 molecular beam epitaxy Methods 0.000 abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 239000012535 impurity Substances 0.000 abstract description 8
- 239000002019 doping agent Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a method of manufacturing a semiconductor device.
従来の技術
半導体装置の製造において、分子線エピタキシー(MB
E)が膜厚および不純物濃度の制御性がよいため、MB
E法による半導体装置の製造技術について多くの研究開
発がなされている。(例えば、高校 清著2分子線エピ
タキシー技術、工業調査会、 1984゜)以下、図面
を参照しながら、上述したような従来のMBE法を用い
た半導体装置の製造方法について説明する。Conventional technology In the manufacture of semiconductor devices, molecular beam epitaxy (MB
E) has good controllability of film thickness and impurity concentration, so MB
Much research and development has been conducted on semiconductor device manufacturing technology using the E method. (For example, Bimolecular Beam Epitaxy Technology, written by Kiyoshi High School, Industrial Research Association, 1984).Hereinafter, a method for manufacturing a semiconductor device using the conventional MBE method as described above will be described with reference to the drawings.
第2図はMBE法を用いた従来の半導体装置の製造方法
を説明するための模式図である。第2図において、12
はG a A s基板、13 、14 、15゜16は
それぞれ、Ga、As、Si、Be用のるつぼ、17.
18はそれぞれSi、Be用るつぼのシャッタ、19は
p型成長層、20はn型成長層、21はMBE装置の真
空チャンバーである。FIG. 2 is a schematic diagram for explaining a conventional method of manufacturing a semiconductor device using the MBE method. In Figure 2, 12
13, 14, 15, 16 are crucibles for Ga, As, Si, and Be, respectively; 17. is a GaAs substrate;
18 is a shutter for a crucible for Si and Be, 19 is a p-type growth layer, 20 is an n-type growth layer, and 21 is a vacuum chamber of the MBE apparatus.
この製造方法においては、まず、表面が平坦なG a
A s基板をMBE装置の真空チャンバー内21に入れ
る。G a A s成長を行う際、GaおよびAsのる
つぼ13.14と同時にBe用るつぼ16のシャッタ1
8を開けるとp型G a A sが成長する。In this manufacturing method, first, Ga with a flat surface is
The A s substrate is placed in the vacuum chamber 21 of the MBE apparatus. When performing Ga As growth, the shutter 1 of the crucible 16 for Be is used at the same time as the crucibles 13 and 14 for Ga and As.
8, p-type GaAs grows.
次にBe用シャッタ18を閉じ、Si用シャッタ17を
開けるとn型GaAsが成長する。このようにして縦方
向(成長方向)にpn接合等の構造を作ることができる
。Next, when the Be shutter 18 is closed and the Si shutter 17 is opened, n-type GaAs grows. In this way, a structure such as a pn junction can be created in the vertical direction (growth direction).
発明が解決しようとする問題点
しかしながら、上記のような構成では、不純物濃度等の
制御ができるのは縦方向(成長方向)のみで横方向(面
方向)の制御は不可能であるという欠点を有していた。Problems to be Solved by the Invention However, the above configuration has the disadvantage that impurity concentration etc. can only be controlled in the vertical direction (growth direction) and cannot be controlled in the lateral direction (plane direction). had.
本発明は上記欠点に鑑み、横方向にも不純物濃度等の制
御ができる半導体装置の製造方法を提供するものである
。In view of the above drawbacks, the present invention provides a method for manufacturing a semiconductor device that allows control of impurity concentration, etc., also in the lateral direction.
問題点を解決するための手段
上記問題点を解決するために、本発明の半導体装置の製
造方法は、基板にSio2.Si3N4等の絶縁膜を形
成し、選択的に上記絶縁膜および基板をエツチングした
後、導電型を決定する不純物の分子線を上記基板に対し
て斜め方向から入射させてMBE成長するということか
ら構成されている。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes a method of manufacturing a semiconductor device using Sio2. After forming an insulating film such as Si3N4 and selectively etching the insulating film and the substrate, MBE growth is performed by making impurity molecular beams that determine the conductivity type obliquely incident on the substrate. has been done.
作 用
この構成により、MBE成長において、分子線は盲進性
かあるために、エツチングで窪みとなった部分では、側
壁により一方の導電型決定間の不純物の分子線がマスク
される領域ができ、1回の成長で横方向にp型、n型あ
るいはi型の成長層を作製することができる。Effect: With this configuration, in MBE growth, since the molecular beam has a blind propagation property, in the part that becomes a depression due to etching, a region is created where the molecular beam of the impurity between one conductivity type determination is masked by the side wall. , a p-type, n-type, or i-type growth layer can be produced in the lateral direction by one growth.
実施例
以下、本発明の一実施例について、第1図を参照しなが
ら説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.
第1図(、) 、 (b)は本発明の一実施例における
半導体製造方法を説明するだめの模式図を示すものであ
る。本実施例では半導体材料としてG a A sを用
いて説明する。第1図(、)および同要部100を示す
同図(b)において1はGaAs基板、2はSio2等
のCVD法により形成された膜、3はG a A s多
結晶膜、4〜7は分子線を発生させるるつぼで4はGa
用、5はAs用、6はSi用、7はBe用である。8は
MBE装置の真空チャンバーである。FIGS. 1(a) and 1(b) are schematic diagrams for explaining a semiconductor manufacturing method according to an embodiment of the present invention. This example will be explained using GaAs as the semiconductor material. In FIG. 1(,) and FIG. 1(b) showing the same essential part 100, 1 is a GaAs substrate, 2 is a film formed by CVD method such as Sio2, 3 is a GaAs polycrystalline film, 4 to 7 is a crucible that generates molecular beams, and 4 is Ga
5 is for As, 6 is for Si, and 7 is for Be. 8 is a vacuum chamber of the MBE apparatus.
また9、10.11はそれぞれp型、n型、i型の成長
層である。Further, 9, 10, and 11 are p-type, n-type, and i-type growth layers, respectively.
先ずG a A s基板1の全面にS x O2ノCV
D膜2をつけた後、選択的にCVD膜2をエツチング
し続いて選択的にG a A s基板1を数1100n
エツチングし窪みを作る。次に上記処理を行ったG a
A s基板1をMBE装置の中に設置し、成長を行う
。First, a CV of S x O2 is applied to the entire surface of the GaAs substrate 1.
After applying the D film 2, the CVD film 2 is selectively etched, and then the GaAs substrate 1 is selectively etched by several 1100 nanometers.
Etch and make a depression. Next, G a after performing the above processing
The As substrate 1 is placed in an MBE apparatus, and growth is performed.
この際St分子線とBe分子線をウェハ面内180゜の
方向から入射すると、窪み内の中央付近では、p、n両
方のドーパントの分子線か照射されるため、i型半導体
となるが、ドーパント入射方向の側壁では、分子線が側
壁によυマスクされるため、p又はn型半導体となる。At this time, when the St molecular beam and the Be molecular beam are incident from a direction of 180 degrees within the wafer plane, the area near the center of the depression is irradiated with both p and n dopant molecular beams, resulting in an i-type semiconductor. On the sidewall in the dopant incident direction, the molecular beam is masked by the sidewall, so it becomes a p- or n-type semiconductor.
以上のように本実施例によれば、基板の選択エツチング
により窪みを作った後、MBE成長を行うことにより、
横方向にp型、n型、i型巣結晶を同時に形成すること
ができる。ここで窪みの深さ2幅を変化させると数種類
のpn接合を実現でき、配線を行うだけで、発光素子、
受光素子、太陽電池などを作製できる。また、拡散、イ
オン注入等の他のプロセスと組み合わせることにより、
半導体集積回路に応用することもできる。As described above, according to this embodiment, by performing MBE growth after forming a depression by selectively etching the substrate,
P-type, n-type, and i-type nest crystals can be formed simultaneously in the lateral direction. By changing the depth and width of the recess, several types of pn junctions can be realized, and just by wiring, light emitting elements,
Light-receiving elements, solar cells, etc. can be created. In addition, by combining with other processes such as diffusion and ion implantation,
It can also be applied to semiconductor integrated circuits.
また成長の際、不要のGa A s多結晶膜がCOD膜
上に付着するがG a A tz多結晶はHCA 等
により容易に除去できる。Further, during growth, an unnecessary GaAs polycrystalline film is deposited on the COD film, but the GaAtz polycrystalline film can be easily removed by HCA or the like.
なお本実施例では、基板およびエビ層ともG a A
sとしたが、I nP 、 AffiGaAs 、 S
i 等測でもよい。In this example, both the substrate and the shrimp layer are G a A
s, but InP, AffiGaAs, S
i may be equal.
ただし材料に応じてドーパントの種類も適当に選ぶ必要
がある。また基板とエピタキシアル層の材料は基板と異
なる材料でもよい。However, it is necessary to select the type of dopant appropriately depending on the material. Further, the material of the substrate and the epitaxial layer may be different from that of the substrate.
発明の効果
以上のように本発明は、基板をエツチングして窪みを設
けた後にMBE成長することにより、横方向に不純物制
御ができ、その実用的効果は大なるものがある。Effects of the Invention As described above, in the present invention, impurities can be controlled in the lateral direction by etching a substrate to form a depression and then performing MBE growth, which has a great practical effect.
【図面の簡単な説明】
第1図は本発明の一実施例における半導体装置の製造方
法を説明するための図、第2図は従来の半導体装置の製
造方法を説明するための図である。
1・・・・・G a A ts基板、2・・・・・・S
i O2,3・・・・・・G a A s多結晶膜、
9・・−・・p型成長層、1o・・・・・・n型成長層
、11・・・・i型成長層。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名を丁
1 図
4−(jQ迅う)IX’5−−−As厚ゲ
G−−−3i部り
’y−4巴部 I+
δ−−− X Iす=ラーヤンノ(゛−2−一一み02
f2−−一らハSぶ不文
f3−一一ね序つっぽ。
(G−3e昂り
fl−−−5i用ンYブゲ
イ8−−−BeルIf
19−−−Pダ入1
2ひ−n覧 ′1
122/−°−朽←7t<’−BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional method for manufacturing a semiconductor device. 1...G a A ts board, 2...S
i O2,3...G a As polycrystalline film,
9...p-type growth layer, 1o...n-type growth layer, 11...i-type growth layer. Name of agent: Patent attorney Toshio Nakao and one other person
4-(jQ quick) IX'5---As thickness G---3i part ri'y-4 Tomoe part I+ δ--- -Ichiraha Sbu unwritten f3-11 ne tsupo. n-list '1 122/-°-decay←7t<'-
Claims (1)
基板に対して斜めの方向から分子線を入射させて、上記
凹部の側壁により上記分子線をマスクして、上記凹部内
に性質の相異なる成長層を形成する工程とをそなえたこ
とを特徴とする半導体装置の製造方法。forming a recess on the surface of the semiconductor substrate; making a molecular beam incident on the semiconductor substrate from an oblique direction; masking the molecular beam with the sidewall of the recess; and forming a recess with different properties within the recess; 1. A method for manufacturing a semiconductor device, comprising the step of forming a growth layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29108686A JPS63142812A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29108686A JPS63142812A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63142812A true JPS63142812A (en) | 1988-06-15 |
Family
ID=17764257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29108686A Pending JPS63142812A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63142812A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006038567A1 (en) * | 2004-10-01 | 2006-04-13 | Waseda University | METHOD FOR PRODUCING P-TYPE Ga2O3 FILM AND METHOD FOR PRODUCING PN JUNCTION-TYPE Ga2O3 FILM |
-
1986
- 1986-12-05 JP JP29108686A patent/JPS63142812A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006038567A1 (en) * | 2004-10-01 | 2006-04-13 | Waseda University | METHOD FOR PRODUCING P-TYPE Ga2O3 FILM AND METHOD FOR PRODUCING PN JUNCTION-TYPE Ga2O3 FILM |
JP2006108263A (en) * | 2004-10-01 | 2006-04-20 | Univ Waseda | MANUFACTURING METHODS OF P TYPE Ga2O3 FILM AND PN JUNCTION Ga2O3 FILM |
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