JPS63142730A - Code detection circuit for burst synchronism - Google Patents

Abstract

PURPOSE:To easily correspond without increasing the scale of a circuit by recognizing what number of bit from the head of a corelative detection area a corelative maximum value in the area occurs at and delaying a reference timing by the value so as to obtain a code detecting timing for burst period corresponding to a maximum value detection timing. CONSTITUTION:A size comparison circuit 4 executes the actions of a recognition means for recognizing the number of times that a selection circuit 2 selects correlative value signals 102. When a timing signal generation circuit 6 receives a detection area starting signal 106, it generates a timing signal 107 which shows the completion of the correlative detection area and transmits it to a delay circuit 5. As a result, the delay circuit 5 delays the timing signal 107 by the number of times and transmits it to an output terminal 9 as a code detection signal 108 for burst synchronism. Namely, necessary delay quantity which is needed as a communication system is obtained in the delay circuit 5.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a burst synchronization code detection circuit for detecting a synchronization code in a receiving system of a TDMA (time division multiple access) communication device, and particularly relates to a burst synchronization code detection circuit for detecting a synchronization code in a receiving system of a TDMA (time division multiple access) communication device. This invention relates to a code detection circuit for burst synchronization using correlation maximum value detection.

(Prior Art) Conventionally, as a burst synchronization code detection circuit using detection of the maximum correlation value of synchronization codes, for example, the one shown in FIG. 2 is known. This code detection circuit for burst synchronization is L
Bit shift register 1° and L correlation detection circuits 11
, a magnitude comparison circuit 12 , a timing designation circuit 13 ,
It basically includes a timing signal generation circuit 14.

The L-bit shift register 10 has a data signal input terminal 15.
The received demodulated received data 201 column applied to L(
(L is a positive integer) is bit shifted, and in the process, L tap outputs 202 are sent to the corresponding correlation detection circuits 11, respectively.

The L correlation detection circuits 11 each calculate a correlation value between the received data string related to the corresponding tap output 202 and a synchronization detection code having a preset M (M is a positive integer) bit configuration, and generate a correlation value signal 203. is sent to the magnitude comparison circuit 12.

The magnitude comparison circuit 12 compares the magnitude relationship between the correlation values indicated by each of the L correlation value signals 203 input in parallel, and the correlation detection circuit 1 generates the correlation value signal 203 indicating the maximum correlation.
1 as the magnitude comparison circuit output signal 204. and sends it to the timing designation circuit 13.

The timing designation circuit 13 is the timing signal generation circuit 1
It operates based on the timing signal 205 from 4, decodes the number indicated by the magnitude comparison circuit output signal 204, and outputs it as the burst synchronization code detection signal 206 to the output terminal 1.
Send to 6.

(Problems to be Solved by the Invention) However, in the conventional burst synchronization code detection circuit described above, the amount of delay necessary for the communication system is "L" of the L-bit shift register.

By calculating the correlation value for each of the L tap outputs of this L-bit shift register and knowing the maximum correlation value detection route of the L correlation values using a magnitude comparison circuit, Since the code position for burst synchronization is recognized, there are problems in that the required number of correlation detection circuits increases in proportion to the increase in the amount of delay, and the scale of the magnitude comparison circuit increases.

The present invention was made in view of these conventional problems, and its purpose is to provide a code detection circuit for burst synchronization that can easily be used in communication systems that require a large amount of delay without increasing the circuit scale. Our goal is to provide the following.

(Means for Solving the Problems) In order to achieve the above object, the burst synchronization code detection circuit of the present invention has the following configuration.

That is, the burst synchronization code detection circuit of the present invention includes a correlation detection circuit that calculates a correlation value between a burst-like received data string and a preset synchronization detection code at each timing position within the correlation detection area; a selection circuit that selects one of the storage circuit output and the correlation detection circuit output based on a magnitude comparison result output; a storage circuit that stores the output of the selection circuit and generates a previously stored value as the storage circuit output; a magnitude comparison circuit that compares the magnitude relationship between the memory circuit output and the correlation detection circuit output, and generates the magnitude comparison result output in order to select the output with a larger value;
recognition means for recognizing the number of times the selection circuit selects the correlation detection circuit output; a timing signal generation circuit that generates a timing signal indicating the end of the correlation detection area based on an externally input reference timing signal; the timing signal A code detection circuit for burst synchronization is characterized by comprising: a delay circuit that delays the code by the number of times and sends it out as a code detection signal for burst synchronization.

(Function) Next, the function of the burst synchronization code detection circuit of the present invention configured as described above will be explained.

The correlation detection circuit calculates the correlation value between the burst-like received data string and the preset synchronization detection code at each timing position within the correlation detection area, and sends it to the selection circuit and the magnitude comparison circuit.

The selection circuit selects one of the storage circuit output and the correlation detection circuit output based on the magnitude comparison result output, and sends it to the storage circuit.

The storage circuit stores the output of the selection circuit and sends the previously stored value to the selection circuit and the magnitude comparison circuit.

The magnitude comparison circuit compares the magnitude relationship between the output of the storage circuit and the output of the correlation detection circuit, that is, compares the correlation value one bit before (previous correlation value) with the current correlation value, and selects the one with the larger value. The magnitude comparison result output is generated in order to select an output.

The recognition means recognizes the number of times the selection circuit has selected the correlation detection circuit output, and sends the recognized number of times to the delay circuit.

fif&, the delay circuit delays the timing signal generated based on the externally input reference timing signal by the number of times, and sends it out as a code detection signal for burst synchronization. In other words, the delay circuit obtains the required amount of delay necessary for the communication system, and even when a large amount of delay is required, it can be easily handled.

In summary, according to the burst synchronization code detection circuit of the present invention, the correlation values generated at each timing position within the correlation detection area are serially compared at each timing,
The system recognizes which bit from the beginning of the correlation detection area the maximum correlation value in that area occurs, and delays the reference timing by that area to obtain the burst synchronization code detection timing that corresponds to the maximum value detection timing. Therefore, even if the amount of delay required for the communication system is large, it can be easily handled without increasing the circuit scale.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure shows a code detection circuit for burst synchronization according to an embodiment of the present invention. This code detection circuit for burst synchronization includes a correlation detection circuit 1, a selection circuit 2, a storage circuit 3, a magnitude comparison circuit 4, It basically includes a delay circuit 5 and a timing signal generation circuit 6.

The detection area start signal 106, which is a reference timing signal applied to the control signal input terminal 8, is input as a heliset signal to the storage circuit 3, and is also input to the timing signal generation circuit 6.
I am also inputting it to

The received and demodulated burst-like received data string '101 is input to the correlation detection circuit 1 via the data signal input terminal 7.

The correlation detection circuit 1 calculates the correlation value between the burst-like received data string 101 and a synchronization detection code having a preset M (M is an integer) bit configuration from time TI (correlation detection area start timing) to time TN (correlation detection area start timing). The correlation value signal 102 related to the calculation is sent to the selection circuit 2 and the magnitude comparison circuit 4.

The selection circuit 2 selects one of the storage circuit output signal 104 and the correlation value signal 102 based on the magnitude comparison circuit output signal 105, and sends it to the storage circuit 3 as the selection circuit output signal 103.

The memory circuit N3 is a temporary memory circuit that can be configured with a clip-flop or the like, and is cleared to an initial state at the timing indicated by the detection area start signal 106, and stores the output correlation value (() of the selection circuit 2 in the correlation detection area). 103
) is updated, and the updated stored value is sent to the selection circuit 2 and the magnitude comparison circuit 4 as the storage circuit output signal 104.

The magnitude comparison circuit 4 compares the magnitude relationship between the storage circuit output signal 104 and the correlation value signal 102, and selects the output having a larger value.
Generates 5.

For example, at time T, the storage circuit 3 is reset to the initial state, so first the correlation value signal 102 is determined to be large, which is selected by the selection circuit 2 and stored in the storage circuit 3. Next, at time T2, the magnitude comparison circuit 4 outputs the correlation value signal 102.
(at time T2) and memory circuit output signal 104 (at time T2)
The correlation value signal at time T, which is the correlation value signal at time T, is compared in magnitude, and the one with the larger correlation value at time T or time T2 is stored in the storage circuit.The operation of 0 or more is repeated until time TN. be.

In the process of the above-described repeated operations, in this embodiment, the magnitude comparison circuit 4 performs the operation of the recognition means for recognizing the number of times the selection circuit 2 selects the correlation value signal 102. Assuming that the circuit output signal 105 is a pulse signal, a positive pulse signal is used when instructing selection of the correlation value signal 102, and a negative pulse signal is used when instructing selection of the memory circuit output signal 104, respectively. , the number of occurrences of a positive pulse signal is counted. The counted number of times value signal 109 is sent to the delay circuit 5.

The timing signal generation circuit 6 generates a detection area start signal 1.
06, a timing signal 107 indicating the end of the correlation detection area is generated and sent to the delay circuit 5.

As a result, the delay circuit 5 delays the timing signal 107 by the number of times, and sends it to the output terminal 9 as the burst synchronization code detection signal 108. In other words, this delay circuit 5 obtains the required amount of delay necessary for the communication system.

In this embodiment, the function of the recognition means is the size comparison circuit 4.
However, the present invention is not limited to this. For example, the magnitude comparison circuit output signal 1 is sent to the delay circuit 5.
Of course, the "number of times" may be recognized by giving "05" and shifting the shift register by "the number of times" in the delay circuit 5.

(Effects of the Invention) As detailed above, according to the code detection circuit for burst synchronization of the present invention, correlation values generated at each timing position within a correlation detection area are compared serially at each timing, and The code detection timing for burst synchronization corresponding to the maximum value detection timing is obtained by recognizing the bit number from the beginning of the correlation detection area in which the maximum correlation value occurs in the correlation detection area, and by delaying the reference timing by that area. Therefore, even if the amount of delay required for the communication system is large, it can be easily handled without increasing the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 1... Correlation detection circuit, 2... Selection circuit, 3... Memory circuit, 4... Size comparison circuit, 5... Delay Circuit, 6... Timing signal generation circuit, 7... Data signal input terminal, 8... Control signal input terminal, 9...
... Output terminal of code detection signal for burst synchronization, 1
0...L bit shift register, 11...
... Correlation detection circuit, 12 ... Size comparison circuit, 13 ... Timing specification circuit, 14 ...
...timing signal generation circuit, 15...
Data signal input terminal, 16... Output terminal of code detection signal for burst synchronization, 101... Received data string, 102... Correlation value signal, 103
...Selection circuit output signal, 104...
Memory circuit output signal, 105... Size comparison circuit output signal, 106... Detection area start signal, 1
07... Timing signal, 108...
Burst synchronization code detection signal, 109... Number of times signal, 201... Received data string, 202
......L-bit shift register output signal (tap output), 203...Correlation value signal, 204...
...... Size comparison circuit output signal, 205...
Timing signal, 206... Code detection signal for burst synchronization. Agent: Yoshihiro Yahata, Patent Attorney, /θ5, Book, 4e Takoθ/Y-Storage Code Search Circuit-7 Figure 7

Claims (1)

[Claims] a correlation detection circuit that calculates a correlation value between the burst-like received data string and a preset synchronization detection code at each timing position within the correlation detection area; and a storage circuit output and the correlation detection based on the magnitude comparison result output; a selection circuit that selects one of the circuit outputs; a storage circuit that stores the output of the selection circuit and generates a previously stored value as the storage circuit output; a magnitude of the storage circuit output and the correlation detection circuit output; a magnitude comparison circuit that compares the relationship and generates the magnitude comparison result output in order to select the output with a larger value; recognition means that recognizes the number of times the selection circuit selects the correlation detection circuit output; an external input a timing signal generation circuit that generates a timing signal indicating the end of the correlation detection area based on a reference timing signal; a delay circuit that delays the timing signal by the number of times and sends it out as a code detection signal for burst synchronization; A code detection circuit for burst synchronization, characterized by comprising;