JPS63140559A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a semiconductor memory device having a circuit that applies a potential higher than a power supply potential or lower than a ground potential to a semiconductor substrate.

[Prior art] In general, dynamic random access memory (
Semiconductor storage devices such as DRAM (DRAM) are operated at a potential higher than the power supply potential or lower than the ground potential (these dislocations are
aa) to the semiconductor substrate.
(hereinafter referred to as a Vaa generation circuit section).

FIG. 2(a) is a plan view showing the arrangement of the main parts of a conventional semiconductor memory device having such a Vaa generation circuit section, and FIG. 2(b) is a cross section taken along the line x-y in FIG. 2(a). It is a diagram.

In the figure, a Vaa generation circuit section 2 is formed in a predetermined region of a p-type semiconductor substrate 1 to generate a potential v68 (for example, -3V) lower than the ground potential.

This Vaa generation circuit section 2 provides the 12th position of Va a to the semiconductor substrate 1 by a charge pump composed of a capacitive element formed on the semiconductor substrate 1 and a ring oscillator. Only the area of is shown. In the cross-sectional view of FIG. 2(b), an n-type impurity diffusion layer 21 (hereinafter referred to as
Only the n+ layer) is shown.

CMOS circuit sections 3a and 3b forming memory peripheral circuits such as a human output buffer circuit and a decoder circuit are formed in regions on both sides of the capacitive element of the VilB generation circuit section 2. This CMOS circuit section 3a.

3b is an n-channel type transistor region 4a, 4b and p
In one CMOS circuit section 3a, the p-channel transistor region 5a is the n+ layer 2 of the capacitive element.
In the other CMOS circuit section 3b, an n-channel type transistor region 4b is located adjacent to the n+ layer 21 of the capacitive element.

In the cross-sectional view of FIG. 2(b), one n + type impurity diffusion layer (
(hereinafter referred to as n+ layer) 418.41b and n-well 50
One p + type impurity diffusion layer 51a, 5 of the p channel type transistor 5a, 5b formed in a, 50b
1b (hereinafter referred to as p+ layer). The n-well 50a.

50b is maintained at the li source potential Vcc.

and,? ! The failed memory cell (not shown) is the CMOS circuit section 3a on the semiconductor substrate 1.

3b is formed in an area further outside.

[Problems to be solved by the invention] In the semiconductor memory device (2) having the above configuration, V+s
The substrate potential Vlllll generated by the a generation circuit section 2
appears in the 01 layer 21, which is one terminal of the capacitive element. At this time, electrons may be injected into the semiconductor substrate 1 due to the resistance of the n+ layer 21 or the like. That is, the Vaa generation circuit section 2 can serve as an electron injection source. The electrons injected into the semiconductor substrate 1 in this way are usually recombined within the semiconductor substrate 1, or are kept at the N source potential Vcc and formed in an n-well, which is a large and deep n-type impurity forced region. 5
Although it is absorbed by 0a and 50b (Figure 3 (a))
If it reaches the memory cell portion, it will be absorbed by the n+ layer, which is a storage node, and cause malfunction.

In the conventional semiconductor memory device configured as described above, the n-well 50b existing all around the p-channel transistor region 5b of one CMOS circuit section 3b is the electron injection source of the Vaa generation circuit section 2. Since it is located far from the capacitive element, Vaa
There has been a problem in that electrons injected into the capacitive element of the generation circuit section 2 are not absorbed by the n-well 50b and tend to reach the memory cell section, causing malfunctions.This invention solves the above-mentioned problems. The purpose of this invention is to reduce malfunctions caused by injection of electrons or holes in the above-mentioned semiconductor memory device having a substrate potential generation circuit section.

[Means for Solving the Problems] The semiconductor memory device according to the present invention has a second conductivity type impurity diffusion layer in the CMO3 circuit section so as to be adjacent to the second conductivity type impurity diffusion layer of the capacitive element in the substrate potential generation circuit section. A first conductive channel type transistor region is formed in the first conductive channel type transistor region.

[Function] In the semiconductor memory device according to the present invention, the 2111-th
Since the second conductivity type well is located adjacent to the type 1 impurity diffusion layer, electrons or holes injected in the region of the capacitive element are immediately absorbed by the second conductivity type well.

Therefore, the amount of charge reaching the storage node of the memory cell portion is reduced, and malfunction of the memory due to injected electrons or holes is reduced.

Examples] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a plan view showing the arrangement of main parts of a semiconductor memory device according to the present invention, and FIG. 1(b) is a plan view showing the arrangement of main parts of a semiconductor memory device according to the present invention.
FIG. In the figure, a loop generation circuit section 2 is formed in a predetermined region of a p-type semiconductor substrate 1 to generate a potential Vaa lower than the ground potential (for example, Gf-3V). This Vaa generation circuit part 2 is formed on a semiconductor substrate 1.
A capacitive element and a ring oscillator are formed by forming an impurity diffusion layer thereon, a charge pump is constituted by these capacitive elements and the ring oscillator, and this charge pump provides the Va a '111 position to the semiconductor substrate 1. It is. In FIG. 1(a), only the region of the capacitive element is shown, and in the cross-sectional view of FIG. 1(b), the n-type impurity diffusion layer 21 (hereinafter referred to as n+ In the regions on both sides of the capacitive element of this Vaa generation circuit section 2, CMOS circuit sections 3a and 3b forming memory peripheral circuits such as a human output buffer circuit and a decoder circuit are formed. The CMOS circuit sections 3a, 3b are composed of n-channel transistor regions 4a, 4b and p-channel transistor regions 5a, 5b.
In a region adjacent to layer 21, an n-well 50a.

p-channel type transistor region 5 formed in 50b
CMOS circuit parts 3a and 3b so that a and 5b are located
is formed. The n-wells 50a and 50b are maintained at the power supply potential Vcc. In the cross-sectional view of FIG. 1(b), one of the n-channel transistor regions 4a and 4b is
n+ type impurity diffusion 141a, 41b (n+ layer)
, and one p+ type impurity diffusion layer 51a, 51b (p+ layer) of p channel type transistor regions 5a, 5b formed in n wells 50a, 50b.

A plurality of memory cells (not shown) are formed on the semiconductor substrate 1 in a region further outside the CMOS circuit sections 3a and 3b.

As described above, in this semiconductor memory device, on both sides of the n+ layer 21 of the capacitive element in the Vaa generation circuit section 2, there are n-wells 50a which are deep n-type impurity diffusion layers surrounding the p-channel transistor regions 5a and 5b. , 50b are located, the electrons injected into the semiconductor substrate 1 in the n+ layer 21 of the capacitive element are transferred to the n wells 50a, 50b.
0b, making it difficult to reach the memory part.

Therefore, memory malfunctions due to injected electrons are reduced.

In the above embodiments, the case where an n-well is formed on a p-type semiconductor substrate has been described, but the present invention can also be applied to a case where an n-well is formed on an n-type semiconductor substrate. The same effect as in the above embodiment is obtained.

[Effects of the Invention] As described above, according to the present invention, the first conductive channel type transistor region and its surroundings in the CMOS circuit portion are adjacent to the second conductive type impurity region of the capacitive element in the substrate potential generation circuit portion. By simply arranging the second conductivity type well, it is possible to easily obtain a semiconductor memory device in which memory malfunctions due to injection of electrons and holes are reduced without increasing the area.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing the main parts of a semiconductor memory device according to one embodiment of the present invention, and FIG.
2(a) is a cross-sectional view of a semiconductor memory device shown in FIG. 2(a) is a plan view showing the main parts of a conventional semiconductor memory device, and FIG.
are a cross-sectional view of the semiconductor memory device in FIG. 2(a), and FIG.
FIGS. 8A and 8B are diagrams for explaining the possibility of electron absorption due to the difference in the position of the 0 well. In the figure, 1 is a p-type semiconductor substrate, 2 is a substrate potential generation circuit section, 3a, 3b are CMOS circuit sections, 4a, 4bG,
tn channel type transistor region, 5a. 5b is a 0-channel type transistor region, and 21 is an n-type impurity diffusion layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Yufue 1st 50a, 50b: ntsuz/shi 2nd written amendment of negative procedure (voluntary)

Claims (1)

[Claims] (1) a substrate potential generation circuit section that includes at least a capacitive element formed in a predetermined region on a semiconductor substrate of a first conductivity type and applies a potential higher than a power supply potential or lower than a ground potential to the semiconductor substrate; a CMOS circuit section that configures a predetermined circuit by a second conductive channel type transistor region formed in another region on the semiconductor substrate and a first conductive channel type transistor region provided in the second conductive type well;
In a semiconductor memory device comprising a plurality of memory cells formed in yet another region on the semiconductor substrate, the semiconductor memory device may include a plurality of memory cells formed in another region on the semiconductor substrate, wherein the The second part in the CMOS circuit section
A semiconductor memory device characterized in that a first conductive channel type transistor region is provided within a conductive type well.