JPS63137387A - Ic card memory - Google Patents
Ic card memoryInfo
- Publication number
- JPS63137387A JPS63137387A JP61284631A JP28463186A JPS63137387A JP S63137387 A JPS63137387 A JP S63137387A JP 61284631 A JP61284631 A JP 61284631A JP 28463186 A JP28463186 A JP 28463186A JP S63137387 A JPS63137387 A JP S63137387A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- rewriting
- circuit
- preventing
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Credit Cards Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は再書き込み防止対策が可能な半導体記憶装置を
内蔵したICメモリカードに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC memory card incorporating a semiconductor storage device capable of preventing rewriting.
[従来の技術]
従来、この種のICメモリカードでは、基板内に封入し
た半導体記憶装置への再書き込みを防止するために、切
換回路に接続された機械的スイッチを基板の一部に取り
付けていた。[Prior Art] Conventionally, in this type of IC memory card, a mechanical switch connected to a switching circuit is attached to a part of the board in order to prevent rewriting to the semiconductor storage device enclosed within the board. Ta.
[発明が解決しようとする問題点]
ところで、近年ICメモリカードは薄型に構成する傾向
にあり、1#1I11以下の厚さでは上記のような機械
的スイッチを設けることはきわめて困難となる。[Problems to be Solved by the Invention] Incidentally, in recent years, there has been a tendency for IC memory cards to be made thinner, and if the thickness is less than 1#1I11, it is extremely difficult to provide a mechanical switch as described above.
本発明の目的は機械的スイッチを設けることが困難な1
1n!14以下の基板に再書き込み防止の機能をもたせ
たICメモリカードを提供することにある。The object of the present invention is to
1n! To provide an IC memory card having a board of 14 or less and a function of preventing rewriting.
[発明の従来技術に対する相違点]
上述した従来の機械的スイッチに対し、本発明は基板の
一部を切断することにより再書き込みを、防止するとい
う独創的内容を有する。[Differences between the invention and the prior art] In contrast to the above-described conventional mechanical switch, the present invention has an original content in that rewriting is prevented by cutting a part of the board.
[問題点を解決するための手段]
本発明は複数個の半導体記憶装置を封入したICメモリ
カードにおいて、基板一部の分離切断に伴ない、回路一
部が開放されて前記半導体記憶装置への再書き込みを防
止する再書き込み防止回路を基板内に一体に封入したこ
とを特徴とするICメモリカードである。[Means for Solving the Problems] The present invention provides an IC memory card in which a plurality of semiconductor storage devices are encapsulated, in which a portion of the circuit is opened as part of the substrate is separated and cut, and the circuit is disconnected to the semiconductor storage device. This IC memory card is characterized in that a rewrite prevention circuit that prevents rewriting is integrally enclosed within a substrate.
[実施例] 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第1図において、複数個の半導体記憶装置4と、該半導
体記憶装置4への再書き込みを防止する再書き込み防止
回路5とを基板1内に一体に封入しである。半導体記憶
装置4と再書き込み防止回路5との関係を第2図に示す
。すなわち第2図において、再書き込み防止回路5はP
型MOSトランジスタQ1と、N型MOSトランジスタ
Q2 。In FIG. 1, a plurality of semiconductor memory devices 4 and a rewrite prevention circuit 5 for preventing rewriting to the semiconductor memory devices 4 are integrally enclosed within a substrate 1. As shown in FIG. The relationship between the semiconductor memory device 4 and the rewrite prevention circuit 5 is shown in FIG. That is, in FIG. 2, the rewrite prevention circuit 5
type MOS transistor Q1 and N type MOS transistor Q2.
Q3とを有し、P型MOSトランジスタQ1とN型MO
SトランジスタQ2どの接続点N2に半導体記憶装置4
の書き込み読み出し用端子R/Wを接続するとともに、
接続点N2にN型MOSトランジスタQ3のゲートを接
続し、トランジスタQ1.Q2のゲートの接続点N1に
トランジスタQ3のドレインを接続したものである。さ
らにN型MOSトランジスタQ3のトレインと電源との
途中に対をなす開放端子A、Bを形成し、対をなす開放
端子A、B間を切り取り可能な導体6にて導通させる。Q3, P-type MOS transistor Q1 and N-type MO
At which connection point N2 of the S transistor Q2 is the semiconductor memory device 4 connected?
While connecting the write/read terminal R/W of
The gate of an N-type MOS transistor Q3 is connected to the connection point N2, and the transistors Q1. The drain of the transistor Q3 is connected to the connection point N1 of the gate of the transistor Q2. Furthermore, a pair of open terminals A and B are formed midway between the train of the N-type MOS transistor Q3 and the power source, and electrical continuity is established between the pair of open terminals A and B through a cuttable conductor 6.
そして、この導体6は第1図に示すように分離切断すべ
き特定位置の基板2内に付設したものである。3は半導
体記憶装置4及び再書き込み防止回路5と外部機器との
間における信号授受、電源供給等を行う外部接続端子で
ある。As shown in FIG. 1, this conductor 6 is attached to the substrate 2 at a specific position to be separated and cut. Reference numeral 3 denotes an external connection terminal for transmitting and receiving signals, supplying power, etc. between the semiconductor storage device 4 and the rewrite prevention circuit 5 and external equipment.
実施例において、半導体記憶装置4への書き込みが終了
した時点で基板1のうち特定位置の基板2を分離切断す
ると、基板2と一体の導体6が切り取られ、対をなす端
子A、B間が開放される。In the embodiment, when the substrate 2 at a specific position of the substrate 1 is separated and cut when writing to the semiconductor memory device 4 is completed, the conductor 6 integrated with the substrate 2 is cut out, and the pair of terminals A and B are separated. It will be released.
端子A、Bの部分が開放されると、電源電位に保たれて
いた接点N1は次第に低下しP型トランジスタQ1とN
型トランジスタQ2とにより構成されたインバータ回路
がOFFとなり、接点N2がHIGHからLOWにレベ
ルが変化する。上記の接点N2に半導体記憶装置4の書
き込み読み出し用端子R/Wが接続されているため、該
端子R/Wへの信号入力が阻止され、再書き込みが不可
能となり、ICメモリカードの記憶内容が保持される。When the terminals A and B are opened, the contact N1, which was kept at the power supply potential, gradually drops and the P-type transistors Q1 and N
The inverter circuit constituted by the type transistor Q2 is turned off, and the level of the contact N2 changes from HIGH to LOW. Since the write/read terminal R/W of the semiconductor storage device 4 is connected to the above contact N2, signal input to the terminal R/W is blocked, rewriting is impossible, and the memory contents of the IC memory card are is retained.
尚、前実施例では基板1の縁部に沿う特定位置の基板2
を分離切断するようにしたが、第3図に示すように基板
1の縁部より内側の特定位置の基板2を打法いて分離切
断するようにしてもよい。In the previous embodiment, the substrate 2 at a specific position along the edge of the substrate 1
Although, as shown in FIG. 3, the substrate 2 at a specific position inside the edge of the substrate 1 may be separated and cut.
この場合、基板2が縁部に露出しないため、切り扱いた
部分に物を引掛けたりすることがなくなる。In this case, since the substrate 2 is not exposed at the edge, there is no possibility of objects getting caught on the cut portion.
[発明の効果]
以上説明したように本発明によれば、回路の一部を開放
することにより、半導体記憶装置への再書き込みを防止
する電気的スイッチを採用したため、汎用の薄膜技術を
利用して薄型の基板内に封入することができ、薄型のI
Cメモリカードに再書き込み防止の機能を付与できる効
果を有するものである。[Effects of the Invention] As explained above, according to the present invention, an electric switch is used that prevents rewriting to a semiconductor memory device by opening a part of the circuit, so that general-purpose thin film technology can be used. can be encapsulated in a thin substrate, and the thin I
This has the effect of imparting a rewrite prevention function to the C memory card.
第1図は本発明の一実施例を示すICメモリカードの外
形図、第2図は本発明の再書き込み防止機構を示す回路
の一例を示す図、第3図は本発明の他の実施例を示す外
形図である。FIG. 1 is an external view of an IC memory card showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of a circuit showing the rewrite prevention mechanism of the present invention, and FIG. 3 is another embodiment of the present invention. FIG.
Claims (1)
メモリカードにおいて、基板一部の分離切断に伴ない、
回路一部が開放されて前記半導体記憶装置への再書き込
みを防止する再書き込み防止回路を基板内に一体に封入
したことを特徴とするICメモリカード。(1) IC with multiple semiconductor memory devices encapsulated within the substrate
In memory cards, due to the separation and cutting of a part of the board,
An IC memory card characterized in that a rewrite prevention circuit that prevents rewriting to the semiconductor storage device when a part of the circuit is opened is integrally enclosed within a substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61284631A JPS63137387A (en) | 1986-11-29 | 1986-11-29 | Ic card memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61284631A JPS63137387A (en) | 1986-11-29 | 1986-11-29 | Ic card memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63137387A true JPS63137387A (en) | 1988-06-09 |
Family
ID=17680970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61284631A Pending JPS63137387A (en) | 1986-11-29 | 1986-11-29 | Ic card memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63137387A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0725401A3 (en) * | 1995-02-03 | 1997-12-29 | Kabushiki Kaisha Toshiba | Information storage apparatus and information processing apparatus using the same |
-
1986
- 1986-11-29 JP JP61284631A patent/JPS63137387A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0725401A3 (en) * | 1995-02-03 | 1997-12-29 | Kabushiki Kaisha Toshiba | Information storage apparatus and information processing apparatus using the same |
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