JPS63136850A - Separation controller for multiplexed data - Google Patents

Abstract

PURPOSE:To attain 100% multiplexing efficiency with almost every data speed by attaining a bit destuffing processing in a several multi frames unit. CONSTITUTION:As for a data row having the transmission frame format of a bit length adjustable to a multiplexed speed, the detection of multi frame synchronous bits which lie in respective transmission frames and a demultiplexing processing of respective data channels are uniformly executed in a same circuit, and the interior of a multi frame is made into smaller multi frames in accordance with necessity. The delete processing of stuffing bit at the end of the small multi frames is uniformly executed for various data speed, and respective terminal interface clock signals are phase-synchronized with the small multi frame unit. A terminal interface clock generation part 19 uniformly phase-synchronizes the partition of the interface clocks of respective speed and the small multi frames with the least common multiple timing of plural and different small multi frame frequencies corresponding to various multiplexed data speed. Thus, multiplexing efficiency of data can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to multiplexed data separation control of digital data.

[Conventional Technique vR] FIG. 8 is a diagram showing a frame format with a transmission rate of 1.5441 BPs and a 24-multiframe configuration, as indicated in, for example, CCITT Recommendation G, 704.
(1) is the F bit of 1 bit/frame, and (2) is the data channel of 24 channels from TsI to T3□4, each of which has 8 bits/frame and has 8 bits of BPS in 64. FIG. 9 is a diagram showing how 9600 BPS synchronous data is multiplexed into the transmission frame shown in FIG. 8. In the figure, (3) is a 9600 BPS synchronous data signal, and (4) is a 9600 BPS synchronous data signal. Column (
3) are grouped into 6 bits, F bits per 6 bits, S
Envelope signal sequence (5) is envelope signal sequence (4) with 1 bit for each bit and a total of 2 bits added to form an envelope, and the speed is 876 times 12.8 KBPs.
are multiplexed in envelope units for 5 channels, and 64K[l
The data string (6) made into a PS signal string is a transmission frame in which the BPS signal string (5) is inserted into a 1.544 MBPs rs (time slot) and multiplexed.

Also, Figure 1O shows the data multiplexed as above,
This is an example of the configuration of a device that demultiplexes on the receiving side, and is part of the new data transmission system (2nd printing) published by Sangyo Tosho Co., Ltd.
01 MUX and Do M shown in I36-PI37
This is an excerpt from the receiving section of IX. In the figure, (7
) is a frame synchronization detector unit that searches for the F bit (1) in the received data string and establishes frame synchronization; (8)
(9) is an elastic buffer that temporarily stores received data and ensures timing alignment with subsequent demultiplexing processing.
(10) is a demultiplexing control unit that separates multiplexed data into multiple channels, (10) is a speed conversion buffer that outputs a data string separated by %ff1 in a burst at a constant speed, and (11) is a 64 is a multi-frame synchronization detection unit for establishing multi-frame synchronization using the F' bit in the BPS envelope string.

FIG. 11 is a diagram showing an example of the internal configuration of the speed conversion buffer (lO), in which (10a) is a FIFO (First, -In%F
irst-OuL) memory, (IOb) is the FIFO memory (10a
) is a write control unit that outputs a write signal to the FIFO memory (10a), (IOC) is a read control unit that provides a data read timing signal to the FIFO memory (10a), and (10d) is a control unit that outputs a write signal to the FIFO memory (10a). This is an accumulation amount detection section that detects whether there is a fish.

Next, the operation of the above-mentioned conventional device will be explained. In Fig. 8, the transmission frame length is 193 bits, which includes 1 bit F bit (1) and Ts+ (2) to T112.
4 (2) 8-bit time slots are divided into 24 channels.

Since the transmission speed is 1.544MBPS, 193
The transmission capacity allocated to each one of the bits is +93. Therefore, the allocated transmission capacity of F bit (1) and each T, (2) is: F bit: 8 to BPSX 1 = 8 [lPS each T8
; 8 BPS x 8 = 64 BPS, and data is multiplexed in each TS (2) with 64 BPS as the basic transmission capacity.

Further, the F bit (1) is information used within the multiplex transmission system, and is used as a frame synchronization code indicating the delimitation of each transmission frame, and is not used for multiplexing data from a terminal. The manner in which the synchronized 9600 [] PS signal (3) is multiplexed to each Ts (2) will be explained with reference to FIG. The 9600 BPS signal (3) synchronized with the transmission line clock is
It is sampled by the 960011Z clock synchronized with the transmission line clock and taken into the multiplexing system. Next, divide this 9600BPS signal (3) into 6 bits,
A total of 2 bits, 1 bit F'' bit and 1 bit S' bit, are added before and after it, and the speed is converted to 876 times.
．． 8, create a BPS data string (4). This F”, S
The 8 bits of the nPS data string (4) at 12.8 surrounded by ' are called an envelope. After this, 12.8KBPs
The data string (4) is multiplexed into 5 channels to form 64 BPS data strings (6), which are multiplexed into one Ts (2) having a transmission capacity of 64 KnPS. In addition, each F' bit in the BPS data string (6) in 64 is (: CITT recommendation x,
The other speed signals at 50 are set to BP 64 in the same manner as above.
It is multiplexed into a transmission frame on the basis of S.

An example of the configuration of a device that demultiplexes and outputs data transmitted after multiplexing as described above as data for each terminal will be explained with reference to FIG. 1θ.

The received data output from the line termination device (OCC, OSU, etc.) is detected by the frame synchronization detector (7) with F bit (
The search in step 1) is performed, and when the delimitation of each frame is confirmed, a synchronization probability signal is output to the demultiplexing control section (9). On the other hand, the received data input to the elastic buffer (8) undergoes timing matching with demultiplexing processing and is then output to the speed conversion buffer (10) as multiplexed data. The demultiplexing control section (9) sequentially outputs the demultiplexing gate signals only during a period corresponding to each TS (2). Elastic buffer (8) to speed conversion buffer (10)
Although data is written in bursts, the data is output from the speed conversion buffer (lO) to the subsequent stage as a continuous envelope string of 64 KBPS. The 64 BPS envelope sequence output from the speed conversion buffer (10) is taken into the multi-frame synchronization detection section (11) and
' bit performs multiframe synchronization detection of the 20 full frame sequence. When the multiframe synchronization establishment signal is output from the multiframe synchronization detection unit (11), the demultiplexing control unit (9) that follows it sequentially outputs separation gate signals for five channels, and converts the speed as data for each terminal. Controls writing to the buffer (10). Data writing to the speed conversion buffer (lO) in this final stage is also performed in bursts as in the previous stage, but output is performed continuously as 96008PS data matching the terminal data rate. Note that the separation gate signal for the 64KBPS envelope train is output from the separation control unit (9) for only 6 bit times excluding the F' bit and S' bit, and deletes and demultiplexes the F' bit and S' bit at the same time. It works like this.

Next, a configuration example of the speed conversion buffer (10) will be explained with reference to FIG. The separation gate signal is connected to the write control section (10b
), the FIFO memory (10a)
An M-inclusive signal is output and multiplexed data is taken into the FIFO memory (10a) of a predetermined number of bits. At the same time, the stacking detection section (10d) performs a count-up operation and counts the number of bits written in the FIFO memory (10a). When the accumulation amount detection unit (LOD) determines that a certain number or more of data exists in the FIFO memory (10a), a read permission signal is sent to the read control unit (IOc).
The readout control unit (10c) receives the readout signal and outputs a continuous readout signal at a constant speed to the PIFO memory (IOa).
), the demultiplexed data is output to the next stage. The storage amount detection unit (10d) detects the FIFO memory (l
The reason why a read enable signal is not outputted until a certain amount of data in oa) is accumulated is to prevent bit slips from occurring on the output side due to long-period jitter of the processing clock at the previous stage.

[Problems to be Solved by the Invention] Since the conventional multiplexed data demultiplexing control device is configured as described above in relation to its data multiplexing format, two stages of demultiplexing processing with different processing timings are required. Therefore, the circuit scale is inevitably increased due to the necessity of cascading two speed conversion buffers for smoothing the data demultiplexed in burst form.
12008Ps x N series data rate 648PS
Since the envelope is configured to match the sequence, the actual occupation rate of data bits within a time slot becomes less than 75% (678 times), resulting in a reduction in multiplexing efficiency. .

This invention was made to solve the problems mentioned in L. It is possible to separate and output data using only one demultiplexing process and one stage of speed conversion buffer, and it also allows data to be separated and output using only one demultiplexing process and one stage of speed conversion buffer. By adding and deleting stuff bits as necessary only once every several multi-frames, the efficiency of converting data is improved, and the process of deleting stuff bits can be performed using a simple configuration. The purpose is to obtain a control device.

[Means for Solving the Problems] The multiplex data separation control device according to the present invention has a data string that has a transmission frame format with a bit length that is easy to match the multiplexing speed. Detection of the multiframe synchronization bit and demultiplexing processing for each data channel are performed in the same circuit, and this multiframe is further divided into smaller multiframes as necessary, and the Stuff bit deletion processing is uniformly performed for various data rates, and the clock signals for each terminal interface are phase-synchronized in units of this small multiframe.

[Operation] The terminal interface clock generation unit of the present invention uses the least common multiple timing of a plurality of different small multi-frame synchronizations corresponding to various multiplexed data speeds to adjust the phase of the interface clock of each speed and the break of small multi-frames. Synchronization is uniformly performed and stuff bits can be deleted using a speed conversion buffer with a simple configuration.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 7 as a transmission frame format having a 320-bit length structure. In Figure 1, (12) is “l
”, 1-bit frame synchronization bit FA that inserts a “0” alternating pattern into each frame, (13) is header information,
(I4) is a control data link, (15) is a 1-bit multiframe synchronization bit F for multiframe synchronization,
, (16) is the time slot for the multiplexed data channel set per frame of each channel in the multiplexed channel provided with N channels, and (17) is the check bit ECC (check word) of the error correction code. .

Figure 2 shows the correspondence between transmission frame synchronization and line capacity per bit when 64 is BPSXN (N = 1 to 6 (7) integer) and the transmission frame length is 320 bits. In the case of PS, the transmission frame length is 32
The case where 0 bit x 7/8 = 280 bits is shown.

FIG. 3 shows an example of the configuration when demultiplexing data strings in the transmission frame format shown in FIGS. 1 and 2. In the figure, (7) is the frame synchronization bit FA in the transmission frame. (12) is a frame synchronization detection unit that searches for frame synchronization, (8) is an elastic buffer that temporarily stores received data, and (9) is a multiplexer that separates multiplexed data by a predetermined number of bits. The separation control unit (lO) is a speed conversion buffer that smoothes the data of each channel separated into bursts and outputs it to the terminal side (
+ 1) is a multiframe synchronization detection unit that takes in the multiframe synchronization bit FB (15) in the transmission frame to obtain multiframe synchronization, and (20) is the multiframe synchronization bit F. A small multi-frame pulse generator (18) generates a signal for further dividing the multi-frame established by the column into small multi-frames, and (18) smoothes the jitter component of the received clock including jitter from the line, and (19) is a clock generation unit that generates an interface reference clock that has a certain synchronization relationship with the clock; (19) is a terminal interface clock generation unit that divides the interface reference clock to generate interface clocks of various speeds; (21) is a terminal interface clock generation unit that generates interface clocks of various speeds; This is a minute set circuit that initializes the terminal interface clock generation unit (19) by synchronizing small multi-frames.

FIG. 4 shows an example of the internal configuration of the speed conversion buffer (lO) in the present invention, in which (10e) is 2
(10f) is a write address counter that specifies the write address for the double memory (10e), and (10g) specifies the read address for the double memory (IOc). Read address counter, (IOh
) is an R/W bank select unit that switches read/write of the double memory (toe), and (10i) is a selector that outputs read data from either one of the double memories (IOe) to the outside.

FIG. 5 is a diagram showing the operation of the rate conversion buffer (lO) in the present invention, and shows the destuffing operation when stuff bits are present in every three transmission frames.

Figure 6 shows the terminal interface clock generator (19)
This figure shows the configuration of the division set circuit (21), in which (19a) is an independently arranged frequency division counter that outputs frequency divisions such as various terminal interface clocks, (
21a) is a set/reset type <5 flip-flop, and (21b) is a D type flip-flop.

Figure 7 shows the frame synchronization detection unit (11) in this embodiment.
In the figure, (lla) is a multi-frame synchronization bit F, an 8-bit shift register that takes in (+5) columns, and (llb) is a pattern matching that detects the multi-frame synchronization pattern. The circuit (Ilc) is a multiframe synchronization protection unit that prevents erroneous synchronization pull-in in multiframe synchronization, and (lid) is a gate that stops output when multiframe synchronization is established.

FIG. 12 shows an example of the configuration of the demultiplexing control unit (9) in this embodiment. In the figure, (9a) is a slot number counter that counts the time slot number for which demultiplexing is performed, and (9b) is a slot number counter for each time slot. (9c) is a separation bit length counter that counts the separated bit length for each time slot; (9d) indicates when separation for a predetermined bit length has been completed. (9e) is a decoder that sequentially outputs M-tree separation gate signals based on N-tree separation slot number signals; (9f) is a gate that controls the output of separation gate signals. .

FIG. 13 shows an example of the configuration of the small multi-frame pulse generator (20) in this embodiment, in which (20a) is a divide-by-5 counter that divides the frame synchronization signal, (20b) is a divide-by-3 counter, (20c) is a divide-by-2 counter, (20
d) is a selector that outputs small multi-frame pulses for minute set circuits based on a combination of line speed and multiplexed terminal data rate.

Next, the operation of this embodiment based on the configuration described above will be explained. In FIG. 1, when the transmission frame length is 320 bits, the transmission capacity allocated to one bit in the transmission frame is determined by the following equation.

C=T,/320 [BPS] However, T5 is the transmission speed [BPS]. According to this, the allocated capacity per 1 bit/frame corresponding to a transmission rate of 64 KBPS x N (N = 1 to 6) is calculated as shown in Figure 2, and the transmission frame synchronization is also entered in Figure 2. It is. Regarding the transmission speed of 56KBPS, the allocated capacity of 1 bit/frame is 6
The transmission frame length is set to 280 bits to be similar to the 4KBPSX N series.

From now on, the allocated capacity per bit/frame will be 200.
xN (N=1 to 6) [BPS], which is the interface speed with a commonly used terminal, 1200.
2400.4800.7200.9600.19.2, 12008PS series such as 48K [BPS] and audio PC
The relationship between data speeds such as 32 and 64 [BPS] used for M and allocated capacity is not necessarily an integer ratio, but every 2 frames, every 3 frames, 5
When considered in units of frames, it can be seen that it is an integer ratio. The relationship at this time is expressed by the following equation.

Here, Y is the data interface speed with the terminal, n is the number of bits multiplexed in one transmission frame, and C is 1 bit/
The allocated transmission capacity per frame, m means multi-frame synchronization when stuffing bits are added, and t means the number of effective bits (nXm - number of stuff bits) among the number of bits allocated for multiplexing during multi-frame synchronization. An example of an apparatus configuration for demultiplexing data strings multiplexed in this manner will be explained based on FIG. 3. In the figure, the frame synchronization detection unit (7) detects the delimitation of each frame in the 64KBPSxN received data string received from the line in the same way as in the conventional example, and the frame synchronization establishment signal is transmitted to the demultiplexing control unit (7). 9) and becomes 0.

On the other hand, the multiplexed data taken in internally via the elastic buffer (8) is demultiplexed sequentially by a predetermined number of bits by a separation gate signal from the demultiplexing control section (9). Until the establishment signal is output from the multi-frame synchronization detection unit (11), the CH is
~C[The demultiplexing control unit is configured so that the demultiplexing gate signal for the time slot (16) for each of the 18 S multiplexed data channels is not output, and only the demultiplexing gate signal for the multiframe synchronization bit FB (15) is output. (9) works. When the multiframe synchronization detection unit (11) confirms the establishment of multiframe synchronization for the multiframe synchronization bit FB(+5) sequence, a multiframe synchronization establishment signal is output to the demultiplexing control unit (9). Upon receiving this multi-frame synchronization establishment signal, the demultiplexing control unit (9) receives the head information (13), the control data link (14), and the G1
Start outputting separation gate signals for time slots (16), etc. for each multiplexed data channel of 11 to CHN,
Demultiplexing of each data channel is performed in bursts, and C
The data of the time slot (16) for each multiplexed data channel I, ~CIIN is written to the rate conversion buffer (10). On the other hand, the reception clock that is normally supplied with jitter is subjected to jitter suppression in the clock generation section (18), and based on this, the interface reference clock that has a certain synchronization relationship with the reception clock, such as 5.
76MH2 is output. This interface reference clock is the terminal interface clock generator (1
9), the predetermined frequency division is performed and +200H2,2400
It is output as a terminal interface clock such as Hz.

Further, the small multi-frame pulse generation section (20) divides the transmission frame timing signal, that is, the frame pulse, based on the minute round set signal timing output from the multi-frame synchronization detection section (11), and divides the frequency of the transmission frame timing signal, that is, the frame pulse. Outputs small multi-frame pulses such as At this time, the minute rotation set signal output from the multiframe synchronization detection section (11) indicates that multiframe synchronization has not been established and a multiframe synchronization pattern is found in the bit string of multiframe synchronization bits F (15). is output when the
- Not output after multiframe synchronization is established once. Further, multiframe synchronization using multiframe synchronization bit F, (+5) is preset as 30, which is the least common multiple of 2.3.5 multiframes. These small multi-frame pulses are stored in a rate conversion buffer (10
) is supplied to perform stuff bit deletion operation, and is regenerated as a reset signal in the minute setting circuit (21), and processed so that the terminal interface clock and the small multi-frame synchronization have a constant phase synchronization relationship. . Data that has been demultiplexed and subjected to destuffing processing is continuously outputted from the speed conversion buffer (lO) in synchronization with the interface clock.

An example of the configuration of the speed conversion buffer in this embodiment will be explained with reference to FIG. In the figure, multiplexed data is memory #1
and memory #2, and the double memory (10e) consisting of these is provided with a predetermined signal in synchronization with the demultiplexing clock during the period when the separation gate signal is input to the write address counter (+Of). Import data for the number of bits. Which of the two double memories (10e) of memory #1 and #2 will be written with data is determined by the instruction from the R/W bank select section (10h). A write address and a write signal are given only to memory (IOe). On the other hand, data is read out continuously in synchronization with the terminal interface clock from the double memory (10e,) designated for reading by the R/1 bank select section (10h). At this time, predetermined read address information is given to the double memory (loe) from the read address counter (10g). Since there are two systems of read data, one on the memory #1 side and one on the memory #2 side, the selector (10i) outputs only one of the data to the subsequent stage with support from the R/19 bank select section (10h). Also, R/W bank select section (LOH)
alternately switches between writing and reading using small multi-frame synchronization pulses determined by line speed and terminal interface speed.

Figure 5 shows the destuffing operation every three multi-frames in a double memory that switches every small multi-frame as shown in Figure 4, and the m-bit data multiplexed in each transmission frame is At the timing of the signal, m bits are separated into bursts and written to the speed conversion buffer (10). At this time, n in 3 transmission frames
Even if a stuff bit exists, it is written into the speed conversion buffer (10) without being considered as a stuff bit like other valid bits. On the other hand, the double memory (TOE) in the speed conversion buffer (10) alternately switches between reading and writing every 3 transmission frames, and immediately after switching to the reading side, mX3-bit data exists inside. . In this m×3 bit data, stuff bits and n bits also exist at the same time. At this time, the number of clocks of the terminal interface clock is M=
If read is performed after selecting m Become.

In order to perform destuffing reliably in this manner, it is necessary that the switching timing of the double memory (10e) for each small multi-frame pulse and the phase of the readout interface clock are aligned.

Figure 6 shows an example of a circuit configuration for achieving this phase synchronization. In the figure, a plurality of frequency division counters (19a) each divide the interface reference clock at a constant frequency division ratio and output a predetermined terminal interface clock. do. In addition, the small multi-frame pulse is transmitted through the RS flip-flop (21a
) to generate a reset request signal. This reset request signal is sampled by the interface reference clock and becomes a reset signal synchronized with the interface reference clock. This reset signal reloads the plurality of frequency division counters (19a) to the initial pattern and starts frequency division again. The reset signal is sampled again by the D-type flip-flop (21b) at the subsequent stage, and the RS
The reset request is canceled by resetting the flip-flop (21a). Furthermore, since the reference clock for the interface uses a value of 5.76 MIIZ, for example, even if the timing of the small multi-frame pulse and the terminal tenter face clock are out of phase, the difference is +70 nS (1
The maximum is about 15,76MH2), which is 1 even if the terminal interface clock is 64+12.
Since the jitter is only about %, it is not a problem in practice.

Next, the operation of the multi-frame synchronization detection section (11) will be explained with reference to FIG. 7 showing a configuration example. The multiplexed data that has not undergone demultiplexing processing is taken into an 8-bit shift register (Ila) bit by bit in synchronization with the demultiplexing gate signal.
This becomes a data string of multi-frame synchronization bit FB (15). This multi-frame synchronization bit FB (15) sequence is detected as a multi-frame synchronization pattern by a pattern matching circuit (1lb). This multi-frame synchronization pattern consists of an 8-bit normal phase pattern and its inverted pattern, and is multiplexed in advance so that it appears alternately every 15 multi-frames. Pattern matching circuit (ll
Both the normal phase pattern detection signal and the reverse pattern detection signal output from b) are input to the multi-frame synchronization protection unit (ILC), and after it is confirmed that both signals appear alternately at each predetermined transmission frame timing period, A signal indicating the synchronization state is output. Multi-frame synchronization holding unit (llc
) stops operating until multi-frame synchronization is not established and a positive phase synchronization pattern is not detected. When the positive-phase pattern detection is output from the pattern matching circuit (Ilb), it passes through the gate (lld) to initialize the multi-frame synchronization protection unit (IIc) and transition to the multi-frame synchronization search state. Subsequently, when the inverted pattern detection state is reached, multi-frame synchronization' is established and the gate (tt
d) Close.

FIG. 12 shows an example of the configuration of a demultiplexing control unit (9) that generates and outputs a demultiplexing gate signal, and a slot number counter (9a) reset by a frame synchronization signal indicating the delimitation of a transmission frame is a time slot that is being demultiplexed. N-tree signals indicating numbers are output as slot number 0. at the same time,
This frame synchronization signal triggers the separate bit length counter (
9C) is also reset and outputs "0" as a count value, indicating that the separation at slot number O has not been executed yet. Separate bit length storage unit (9b
), N output from the slot number counter (9a)
A comparator (9d
). When the separation process starts and the separation bit length counter (9C) starts counting, the output from the separation bit length storage unit (9b) and the separation bit length counter (9C)
The comparator (9d) which receives the outputs from and monitors both signals until they match. The separation process continues and the comparator (9
When the two input signals to d) match, the comparator (9d) passes the matching signal output to the separation bit length counter (9C) and the slot number counter (9a) to notify that the separation for the time slot has ended. . This comparator (9d
) The match signal output from the separate bit length counter (9c)
and slot number counter (9a).
is incremented by 1 and the separation processing for the next time slot is started. By sequentially performing this operation, the separated slot number signal N tree from the slot number counter (9a) holds each pattern for a time corresponding to a predetermined bit length. On the other hand, in the decoder (9e), N
It operates so that only one tree out of M output signals is made valid in accordance with the input signal pattern. Since these N human input signals are signals of the slot number being separated from the slot number counter (9a), the output signal from the derader (9e) can be used as is as a separation gate signal. However, separation processing is meaningless in the state where reception and transmission frame synchronization has not been established, so the decoder (
9e) operates to invalidate all M output signals until a frame synchronization establishment signal is input manually. Once the frame synchronization establishment signal is input, the M output signals become valid in sequence and are passed to the outside.However, until multiframe synchronization is established, a gate ( 9 [) closes. In this way, through a series of operations, the isolation gate signals of each section are sequentially output for a predetermined bit length.

In addition, FIG. 13 shows the small multi-frame pulse generator (20
) shows a configuration example of a 5-divider counter (20a), 3, which is reset by a minute-round set signal.
Frequency division counter (20b), 2 frequency division counter (20c)
) divide the frame synchronization signal by 5/3/2, respectively.

The output of each of these frequency division counters is multiplied (ANDed) with the frame synchronization signal, shaped into a signal with the same time width as the frame synchronization signal, and output as 5/3/2 multiframe pulses to each section. be done. On the other hand, the selector (
20d), a 5/3/2 multiframe pulse and a frame synchronization signal (also referred to as 1 multiframe pulse) corresponding to the line speed and multiplexing format at that time.
Among them, a small multi-frame pulse that is the least common multiple of those actually used is selected and output as a small multi-frame pulse for the minute rotation set circuit.

Note that in the above embodiment, the multi-frame synchronization detection unit (11
), depending on the presence or absence of the multiframe synchronization establishment signal from
Although the configuration was configured such that the separation gate signal output from the demultiplexing control unit (9) is selectively outputted and unnecessary data is not written to the speed conversion buffer (lO) in the state where multi-frame synchronization is not established, all separation gate signals are always output. It may be configured such that the data is output for a time slot of 1 and that the data output is stopped when multi-frame synchronization is not established on the read side of the speed conversion buffer (lO).

Furthermore, the minute rotation set circuit (21) includes one RS flip-flop (21a) and two D-type flip-flops (21a) and two D-type flip-flops (21a).
1b), the reset signal was configured to be synchronized with the interface reference clock, but the synchronization time of the interface reference clock was sufficiently long (for example, 5 times).
By generating a multi-frame pulse with a small width, a differentiator may be configured using two D-type flip-flops and an AND circuit.

[Effects of the Invention] As described above, according to the present invention, since the demultiplexing process and the speed conversion process are each performed in one stage, it is possible to reduce the circuit scale. Accordingly, maintenance and adjustment can be easily performed. Furthermore, since the structure is configured so that bit destuffing can be performed as necessary in units of several multi-frames, 100% multiplexing efficiency can be achieved at almost any data rate, and the multiplexing efficiency does not deteriorate.

[Brief explanation of the drawing]

FIG. 1 is a transmission frame configuration diagram showing the data multiplexing format handled by the multiplexed data separation control device according to the present invention, and FIG. 2 is a transmission frame configuration diagram showing the transmission frame configuration shown in FIG. A diagram showing
FIG. 3 is an internal configuration diagram of a multiplexed data separation control device according to an embodiment of the invention, FIG. 4 is a configuration diagram of a speed conversion buffer according to an embodiment of the invention, and FIG. 5 is an embodiment of the invention. Operation timing diagram of speed conversion buffer by
The figure shows an example of the configuration of a terminal interface clock generation section and minute rotation set circuit according to an embodiment of the present invention, FIG. 7 is a configuration diagram of a multi-frame synchronization detection section according to an embodiment of the present invention, and FIG. FIG. 9 is a frame configuration diagram showing an example of conventional multiplexing processing; FIG. 1O is an internal configuration diagram of a conventional multiplexed data separation control device; FIG. FIG. 12 is a configuration diagram of a conventional speed conversion buffer, FIG. 12 is a configuration diagram of a demultiplexing control section according to an embodiment of the present invention, and FIG. 13 is a configuration diagram of a small multipulse generation section according to an embodiment of the present invention. It is. In the figure, (1) is the frame synchronization bit F, (2) is the time slot for multiplexed data channel, and (3) is the time slot for multiplexed data channel.
) is 9600 BPS data, (4) is 12.8 BPS
data, (5) is 64 BPS data, (6) is 1.5
44MBPS data, (7) is a frame synchronization detector section, (8) is an elastic buffer, (9) is a demultiplexing control section, (9a) is a slot number counter, (9b) is a separation bit length storage section, (9C ) is a separate bit length counter, (9d) is a comparator, (9e) is a decoder, (
9f) is the gate, (10) is the speed conversion buffer, (loa) is the FIFO memory, (tab) is the write control section, (10c) is the read control section, (IOd) is the storage amount detection section, (10e) is the double Memory, (tor> is the write address counter, (10g) is the read address counter, (loh) is the R/■ bank select section, (lOi) is the selector, (11) is the multi-frame synchronization detection section, (I la) is 8-bit shift register, (Ilb) is a pattern matching circuit, (llc) is a multi-frame synchronization protection unit, (
(lid) is a gate, and (12) is a frame synchronization bit FA. (!3) is header information, (14) is control data link, (15) is multiframe synchronization bit FB/(16)
is the time slot for the multiplexed data channel (17) is the check word of the error correction code, (18) is the clock generator, (19) is the terminal interface clock generator, (+
9a) is a frequency division counter, (20) is a small multi-frame pulse generator, (20a)
is a divide-by-5 counter, (2Qb) is a divide-by-3 counter, (20c) is a divide-by-2 counter, (20d) is a selector,
(21) is a minute rotation set circuit, (21a) is an RS flip-flop, and (21b) is a D-type flip-flop. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A fixed length transmission frame of 320 bits x M (M is an integer of 1 or more) is detected with frame synchronization for a transmission rate of 64KBPS x N (N is an integer of 1 or more), and the detected fixed length transmission frame is In a multiplex data separation control device that separates long transmission frames and outputs them as independent data, the above 320 bits x M fixed length transmission frame x K (K is 1
a multi-frame synchronization detection unit that detects multi-frames by synchronizing each frame (an integer greater than or equal to A speed conversion buffer formed by a frame pulse generation unit that generates a frame pulse, and a double buffer for outputting terminal interface data whose reading and writing are alternately switched based on the small multi-frame pulse generated by the frame pulse generation unit; Multiplexed data characterized in that it is configured to include a terminal interface clock signal generation section that generates a terminal interface clock signal that samples the output data at the read/write switching timing of the speed conversion buffer. Separation control device.