JPS63136228A - Document processor - Google Patents

Abstract

PURPOSE:To simplify implantation of programs developed by different document processors and to shorten the periods of development of those programs, by providing a mapping circuit and changing the mapping contents when the programs are implanted. CONSTITUTION:A CPU 1 selected a corresponding program out of a memory 2 by means of the functions selected by a keyboard 31, a mouse 32, etc., and at the same time selects he corresponding mapping data in a memory part 1a to store it in a mapping circuit 140. The circuit 140 maps the address signal received from the CPU 1 into an optional address as necessary and then converts a logical address into a physical address to send it to each module via a bus 10. When a filing function, for example, is selected, the CPU 1 judges a standard program via the circuit 140 selects a using position in the memory 2 to read out the contents of the program. Then the CPU 1 loads a control program to execute the corresponding program and carries out the basic operation of the filing function.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a document processing device such as a document filing device that freely combines and processes code data and image data.

(Prior Art) In recent years, the efficiency of office work has been improved by using office automation. Among these, for example, document filing devices that electronically file existing paper documents as image data, word processors that create documents or process data using code data, personal computers, and the like have developed and become popular.

In order to effectively utilize these devices in a variety of office tasks, specialized software that is adapted to on-site office work is required. Further, the development requires a huge amount of development cost and development period, which is one of the reasons for making the device expensive.

On the other hand, as the popularity and development of each device progresses, the range of application of each device also expands, and, for example, document creation and data processing are increasingly being performed in document filing units. In this case, in the field where the device is actually used, there is an increasing demand for programs for personal computers, word processors, etc. currently in use to be directly ported to the document filing device and operated.

However, as mentioned above, the development of these programs requires development costs and development time, and there are problems in that the cost of the equipment increases and the programs are not completed at the required time.

In particular, in order to run a program at high speed, it is necessary to create a program that depends on the memory space or device address of each device. For this reason, when attempting to port the program to other devices, a problem arises in that the same level of development cost and time is required for each device.

(Problems to be Solved by the Invention) As mentioned above, the program is redeveloped and ported according to the memory space or device address of each device to which the program is to be ported. This eliminates the disadvantage of increasing the cost of the equipment and making the equipment expensive.It also allows programs developed for different equipment to be easily ported, reduces development costs and development time, and lowers the equipment price. The purpose is to provide a document processing device that can perform

[Structure of the Invention] (Means for Solving the Problems) The document processing device of the present invention includes: a first storage means having control programs for various functions; a control program stored in the first storage means; a second storage means that stores a conversion address corresponding to the first storage means; a control means that performs control according to the control program stored in the first storage means; and a second storage means that performs control according to the control program stored in the first storage means; The processing means reads out the converted address and converts the address supplied from the control means in accordance with the converted address.

(Function) This invention provides a mapping circuit between at least a control means, a memory, and each input/output device, and when porting a program running on a device with a different memory space or device address, the mapping contents of the mapping circuit are provided. It was designed to change the .

<Example> Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a sentence 1 filling device as a document processing device of the present invention. That is, the CPU 1 controls the entire device, and programs stored in the memory 2 are sequentially executed, and filing processing, document processing, Alternatively, it performs data processing, etc.

The CPU 1 has a keyboard 31 or a mouse 32.
Depending on the function selected (filing function, personal computer function, word processing function, etc.), the corresponding program in the memory 2, which will be described later, is selected, and the corresponding mapping data in the mapping data storage section 1a is also selected. Mapping R in the mapping circuit 140 described later
It is designed to be stored in AM147.

The mapping data storage section 1a has mapping data tables corresponding to each of the filing function, personal computer function, and word processing function.

For example, in this embodiment, in response to the filing function, the mapping data regarding the top 16 hits (88 to A23) of the 24-bit address <AO to A23) is "00oOH'', mapping data rooolHJ for address data ``0OO1H'', and rFFFFHJ for address data rFFFF+J are stored.

In addition, address data rooo
“0000H” for OHJ, ~address data rE
Mapping data such as "FCooH" for 400HJ, rFcOIHJ for address data rE401+J, and rFFFFHJ for address data rFFFF+J are stored.

Furthermore, the processed results are displayed on the display 4 via the display control section 41.

Further, the above-mentioned document processing is performed by a character/graphic pattern generation circuit 5 that generates a predetermined character or graphic pattern, and an image processing section 6 that performs image enlargement, reduction, rotation, inversion, movement, and calculation.

On the other hand, the optical disk 7 stores documents and the like as images and transfers the images via the optical disk interface 71, and the printer 8 and scanner 9 input images via the scanner-printer interface 81, respectively. It is used for printing.

Further, the communication control circuit 12 is a LAN (not shown).

Connect to other network systems via facsimile or line, etc. to send and receive code data or image data, or connect to other host computers via communication interfaces (R5-232C1GPIB, 5C3I, etc.) not shown, and use them as terminals. It is something that performs an action.

Further, the system bus 10 is a bus for exchanging data between the CPU 1 and each other module, and is used to exchange addresses, data, or image data.

Further, the mapping circuit 140 is one of the main components of the present invention, and maps an address signal from the CPU 1 to an arbitrary address as necessary. The mapped fusuma address is output to the system bus 10 and given to each other module.

The decoding circuits 130 to 136 decode the address (memory and device address) output to the system bus 10 and compare it with their own address (which can be set arbitrarily) to determine whether or not they have been selected. However, it operates when the result of this judgment is a match.

On the other hand, the image bus 11 is a high-speed bus dedicated to transferring image data when each module uses the image data in addition to the CPtJ1, and is composed of address, data, and control signal buses.

Next, the basic operation of the document filling device will be explained.

First, when creating or editing a document, the user inputs an arbitrary character string from the keyboard 31, converts it into a sentence containing kanji using a program such as kana-kanji conversion stored in the memory 2, and then outputs the result. Display on display 4.

Next, while referring to the character strings displayed on the display 4, the user roughly inputs character strings to create a document, or edits the character strings by moving, deleting, adding, etc. We will create a document.

When the document creation is completed, the user specifies a format such as vertical writing or horizontal writing, and prints it from the printer 8 to create the final document.

Next, a case will be described in which an existing document is searched for or input from the optical disc 7 or the scanner 9, and then the results are displayed on the display 4.

First, when a user searches for a document stored on the optical disc 7, the user uses the keyboard 31 or mouse 3 while referring to the search menu displayed on the display 4.
2, etc., and execute the search process for the required document. 'In this search process, the CPU 1 executes a search process program or a document management program in the memory 2, thereby calculating the track number, sector number, etc. of the optical disk 7 in which the corresponding document is stored.

Based on this search result, image data is read from the optical disc 7 via the optical disc interface 71,
After being decompressed by the image processing section 6, it is displayed on the screen of the display 4 via the display control section 41.

Further, when input from the scanner 9, it is displayed on the display 4 via the scanner printer interface 81 and the image bus 11. At this time, if image processing such as enlargement, reduction, rotation, etc. is required, the image is processed via the image processing section 6 and then displayed on the display 4.

The memory 2 has memory sections 2a, . . . (processing programs) corresponding to filing functions, personal computer functions, word processing functions, etc., and the processing programs to be used are selected by a selection signal from the CPUI. It has become.

As shown in FIG. 3, the memory unit 2a for the document filing function includes a 2M byte main memory in which a program executed by the CPU is stored, a 4M byte page memory as an area for storing image data or code data, VRAM as an area for storing data to be displayed on the display 4, Kanji ROM/RAM as an area for storing kanji patterns, 32KB as an area for storing a program that controls the start of the device after power is turned on. It consists of a byte IPLROM and a reserve area.

In the memory section 2a, [00ooo~1FFFFFJ addresses are the main memory area, r400000~7FFFFFJ addresses are the page memory area, rE40000~E8FFFFJ addresses are the VRAM area, rFEOOOOo~FEFFFFJ addresses are the Kanji ROM/RAM area, rEF8000~FFFFFF
IPLROM area at J address, r200000~3
FFFFFJ address, raooooo~BFFFFF
J address, rFFOOOOo-FF7FFFJ address, and serve area memory map.

Thereby, the CPU 1 executes each process using a program adapted to the memory section 2a, and performs the basic operations described above.

As shown in FIG. 4, the memory unit 2b for personal computer functions includes a 1M byte main memory in which the program executed by the CPU 1 is stored, a 4 byte refresh code memory for display, a palette register, and a display 4 to be displayed. VRAM as an area for storing data to be used, Kanji ROM/RAM as an area for storing kanji patterns, 32K as an area for storing a program that controls the start of the device after power is turned on.
It consists of a B-byte IPLROM and a reserve area.

In the memory section 2b, addresses rooooooo to 0FFFFFJ are the main memory area, addresses rFBOOOo to FBOFFFJ are the display refresh code memory area, and rF
BFFFo~FBFFFFJ addresses are palette register area, rFcOOOo~FDFFFFJ addresses are VRAM area, rFEOOOOo~FEFFFFJ addresses are Kanji ROM/RAM area, rEF8000~FFFFFF
J address is IPLROM area, r100000~3
FFFFFJ address, r400000-FAFFFF
The J address and rFBlooo-FBFFEFJ address form a memory map called a reserve area.

The mapping circuit 140 stores mapping data according to each function supplied from the mapping data storage section 1a by the CPUI, and converts the logical address from the CPU 1 into a physical address according to this mapping data. be. As shown in FIG. 2, the mapping circuit 140 includes an address interface 141, a control interface 142, a data interface 143, a mapping control circuit 144, a write address register 145, a write data register 146, a mapping R
AM147 and system bus interface 14
It is composed of 8.

That is, the 24-bit logical addresses AO to A23 from the CPU 1 are supplied to the address interface 141. Address for the upper 16 bits output from this address interface 141 (A8 to A23)
is supplied to the mapping RAM 147, and the lower 8-bit address (AO-A7) is supplied to the system bus interface 148.

Further, a write signal (4 bits) indicating the blurring of the 4-bit mapping data from the CPU 1 is sent to the mapping control circuit 1 via the control interface 142.
44.

Further, the 16-bit address data and write data from the CP (Jl) are supplied to a write address register 145 and a write data register 146, respectively, via a data interface 143.

The write address from the write address register 145,
The write data from write data register 146 is supplied to mapping RAM 147, respectively.

Further, the write signal from the mapping control circuit 144 is adapted to output a read signal to the mapping RAM 147 in accordance with the address data output from the write address register 145 and the write address interface 141.

As a result, when the mapping RAM 147 is supplied with a write signal from the mapping control circuit 144, the mapping RAM 147 stores the write data supplied from the write data register 146 at the address supplied from the write address register 145, and the mapping control circuit 144 When a read signal is supplied from the address interface 141, the content of the address (16-bit address data) supplied from the address interface 141 is output.

The address data output from the mapping RAM 147 and the 8-bit address data supplied from the address interface 141 are output as a series of data (24 bits) to the system bus 10 via the system bus interface 148. It has become so.

First, writing of mapping data to the mapping circuit 140 will be explained.

That is, first, a write signal from CPU i is supplied to the mapping control circuit 144 via the control interface 142. Also, write address data and write data supplied from the CPU 1 are sent to the write address register 1 via the data interface 143, respectively.
45 and is supplied to the write data register 146. As a result, write address data and write data are set in write address register 145 and write data register 146, respectively. Thereafter, write data is written to the write address of the mapping RAM 147 in response to a write signal from the mapping control circuit 144.

In this way, by sequentially writing data, one unit of standard mapping data corresponding to the filing function, mapping data corresponding to the PC function, or mapping data corresponding to the word processing function is generated. is stored in the mapping RAM 147. However, the mapping RAM 147 stores the standard program (corresponding to the filing function) when a series of processes is started.

For example, a standard program (compatible with filing function)
When executing, roo of mapping RAM 147
oOHJ address: 0OOOHJ, rooo1HJ7 dress: roool
Address data corresponding to the address r1FFF+J is sequentially written to addresses HJ, to rIFFF+J.

In addition, if you want to run a program compatible with PC functions, rE400nJ of the mapping RAM 147
7 do I, t':;1. f'Fc0OHJ, "E401
Address data such as rFcO1+J is sequentially written to the HJ address.

The mapping data may be a device address in addition to a memory address.

Next, reading of the mapping data written to the mapping RAM 147 will be explained.

That is, the upper 16 bits of address data from the CPU 1 are supplied to the mapping RAM 147 via the address interface 141, and the lower 8 bits are supplied to the system bus interface 148. Further, the mapping control circuit 144 outputs a read signal to the mapping RAM 147 based on the address data output from the address ink-face 141.

As a result, the mapping RAM 147 outputs the contents of the address supplied from the address interface 141 to the system bus interface 148. As a result, the system bus interface 148 creates 24-bit address data from the address data supplied from the mapping RAM 147 and the address data supplied from the address interface 141, and outputs it to the system bus 10.

For example, when mapping data (standard program) corresponding to the filing function is stored in the mapping RAM 147, roooos J is stored in response to address data roooo+J supplied from the address interface 141, and "roooos J" is stored in response to "0oO1H". 00
01H'', ~rlFFF+J corresponding to rIFFF, 4
Address data J is sequentially output.

Furthermore, when mapping data corresponding to the PC function is stored in the mapping RAM 147, the upper 16 bits (
rFcOO+J corresponding to address data number rE400+J of A8 to A23), and "FCOl" corresponding to rE401HJ.
Address data rF[)FFHJ is output in response to "H", ~rE8FF, and J.

In this case, as shown in FIG.
The address space (logical address space, physical address space) of 40 is 16M bits, and mapping can be performed using the upper 16 bits of the address data. This allows memory mapping to be performed in units of 256 bits.

Further, since the amount of conversion from a logical address to a physical address via the mapping circuit 140 is 64 bits, the capacity of the mapping RAM 147 is only 256 bytes, resulting in a reduction in circuit scale.

Next, the operation of the above configuration will be explained with reference to the flowchart shown in FIG.

First, a case in which processing is executed using the filing function will be explained. That is, the user selects the 7 filling function using the keyboard 31, mouse 32, or the like. Then, CPI
JI determines the use of the standard program in the mapping circuit 140 by selecting the filing function 3, and selects the use of the memory section 2a of the memory 2.

Next, the CPU reads the contents of the main memory of the memory section 2a and loads the control program. Furthermore, CPIJl executes processing according to the loaded control program and performs the basic operation of the filing function described above.

When loading the above control program, the CPU
The rooo000+J address is supplied from 1 to the address interface 141 in the mapping circuit 140. Then, the address interface 141 outputs the upper 16 bits of the supplied address, rooooon J, to the 7-pin RAM 147, and outputs the lower 8 bits, rooooon
+J is output to the system bus interface 148.

Further, in response to the address output from the address interface 141, the mapping control circuit 144 outputs a read signal to the mapping RAM 147. Then, the mapping RAM 147 receives the roooOH signal supplied from the address interface 141 by the read signal.
roooos J is output to the system bus interface 148 for the J address. As a result, the system bus interface 148 is connected to the mapping RAM 14.
The 24-bit address data roo0000HJ is created from the address data r00+J supplied from the address interface 141 and the address data r00+J supplied from the address interface 141, and is output to the system bus 10.

Next, a case where processing is executed using a personal computer function will be explained. That is, the keyboard 31 or the mouse 32
etc. to select the computer function. Then, by selecting the personal computer function, the CPU determines the use of mapping data corresponding to the personal computer function in the mapping circuit 140, and selects the use of the memory section 2b of the memory 2. This results in
The cPU1 sequentially reads mapping data corresponding to the PC functions from the mapping data storage section 1a and stores it in the mapping RAM 147 in the mapping circuit 140.

That is, first, a write signal from the CPU 1 is supplied to the mapping control circuit 144 via the control interface 142. In addition, write address data and write data supplied from the CPU are sent to the write address register 145 via the data interface 143, respectively.
, are supplied to the write data register 146. As a result, write address register 145, write data register 1
Write address data and write data are set in 46, respectively.

Thereafter, write data is written to the write address of the mapping RAM 147 in response to a write signal from the mapping control circuit 144. By sequentially writing data in this way, one unit of mapping data, that is, mapping data corresponding to a PC function, is stored in the mapping RAM 147.

For example, a write signal from the CPU 1 is sent to the mapping control circuit 144 via the control interface 142.
supplied to In addition, write address data rE400HJ and write data rFcOOsJ supplied from the CPU1
are supplied to a write address register 145 and a write data register 146 via a data interface 143, respectively. As a result, write address register 145
, write address data rE400HJ and write data rFcOOsJ are set in the write data register 146, respectively.

After that, a write signal from the mapping control circuit 144 causes the mapping RAM 147 to be written to L/S rE4.
00HJ t, :ll included 7” - write rFCOOHJ. In this way, rFcOl is written to the address of rE401H-E8FFHJ.
H-FDFF+J data is stored.

As a result, address data rE40000+”E8FFFF1.IJ becomes rFcOO
The address space is OOH to FDFFFFHJ.

Next, the CPU 1 reads the contents of the main memory of the memory section 2b and loads the control program. Furthermore, the cpUi executes processing according to the loaded control program and operates the PC functions.

When using the VRAM area of the memory section 2b, the CPU
1 to the address interface 141 in the mapping circuit 140 are supplied with rE40000H to E8FFFFHJ addresses. Then, the address interface 141 reads the upper 16 bits of the supplied address rE400H-E8.
FFHJ is output to the mapping RAM 147, and the lower 8 bits I"0ON-FFHJ are output to the system bus interface 148. Furthermore, in response to the output of the address from the address interface 141, the mapping control circuit 144 outputs a read signal to the mapping RAM 147. do.

Then, the mapping RAM 147 uses the read signal to read r supplied from the address interface 141.
E400H=E8FFH" rFc for 7t'L/s
Outputs OO+ to FDFFHJ to the system bus interface 148. As a result, the system bus interface 148 creates 24-bit address data rFcOOOO+"FDFFFFHJ from the address data rFcOO+<~FDFFHJ supplied from the mapping RAM 147 and the address data roo+-, -FF+J supplied from the address interface 141, and Output to bus 10.

Therefore, as if it were a document filing device,
r E 40000 H= E 8 F F F F
It operates as if it were accessing the H-i's VRAM, but in the document filing device, the mapping circuit 14
The memory address is converted by 0, the actual VRAM area rFcOOOOOn-FDFFFFHJ is accessed, and display data is written and displayed on the display 4.

As a result, the document filing device can perform processing as if it were operating in the memory space of a personal computer, such as V
It can be drawn on the RAM and displayed on the display 4.

After the processing corresponding to the above computer functions is completed, the CPU
i is the mapping RAM 147 in the mapping circuit 140
Since the data has been changed from the standard, the standard program (manpping data corresponding to the filing function) is read from the mapping data storage section 1a, and the mapping R
Store in AM147. As a result, mapping circuit 1
40 in standard state ()? (setting function).

In addition to the mapping of memory addresses as described above, mapping of device addresses (I10 boat addresses) can also be performed in the same manner as described above. Further, the mapping may be performed for all addresses or may be performed for a certain unit.

As mentioned above, the memory address and device address (or I10 boat address) output from the CPU are mapped and then given to each module, making it easy to program programs developed on devices with different memory maps or I10 maps. It is portable and can reduce development costs and development time.

In the above embodiment, the size of the logical address and the physical address are the same, but the present invention is not limited to this, and even if the sizes are different, they can be handled in the same way. That is, as shown in FIG. 7, even if the system has a physical address space that exceeds the real address space of CPtJ, it can be accessed by the CPU by appropriately setting the mapping data of the mapping circuit.

That is, CPLI has 16M bits (AO to A
Although there is only an address space of 23), the address space is 64M bits (A
It becomes possible to access the address space of O-A27), and it becomes possible to easily process image data using a large capacity memory.

In particular, when a document filing device handles not only monochrome documents but also halftone image documents, color image documents, etc., its image memory may exceed the CPIJ address space.

In such cases, image processing for each plane (for example, R, G, B, or each gradation) or access from the CPU can be performed by simply rewriting the mapping data using a program that handles the same address space. Become. Although FIG. 7 shows an example of bits at 64, the unit can be determined arbitrarily.

Therefore, even if the memory has a physical address that exceeds the real address of the CPU, data can be manipulated! ! By simply changing the image data, it can be accessed by the CPU, and various image processing can be easily performed.

Furthermore, even if the physical address space is smaller than the logical address space, it can be processed by rewriting the mapping data without changing the program, as described above.

Furthermore, a mapping circuit was provided on the system bus side, but
It is also possible to provide the mapping circuit on the image bus side and perform address space mapping on the image bus.

Further, although two systems, a system bus and an image bus, are shown, a single common bus or a multiple bus configuration of three or more buses may be used.

In general, the memory is Dualport memory, DRA
M, and two systems of bus interfaces may be implemented.

In addition, although we have explained the case where the mapping data in the mapping RAM is always used, this is not the only case. In the case of a standard program, for example, in the case of a filing function, the CPU
Address data may be output as is as address data, and in the case of other functions, mapping may be performed using mapping data corresponding to that function to perform processing.

[Effects of the Invention] As detailed above, according to the present invention, programs developed for different devices can be easily ported, development costs and development time can be reduced, and the price of the MliI-rated device can be reduced. It is possible to provide a document processing device that can perform

[Brief explanation of the drawing]

FIG. 1 to FIG. 6 show an embodiment of this invention.
Fig. 1 is a block diagram showing a schematic configuration of a document filing device, Fig. 2 is a block diagram showing a schematic configuration of a mapping circuit, Fig. 3 is a diagram showing an example of a memory map of a memory section for the filing function, and Fig. 4 is a block diagram showing a schematic configuration of a mapping circuit. FIG. 5 is a flow chart for explaining the operation, FIG. 6 is a diagram for explaining the relationship between the logical address space and the physical address space, and FIG. FIG. 7 is a diagram for explaining the relationship between a logical address space and a physical address space in another embodiment. 1...CPU, 1a...Mapping data storage unit,
2...Memory, 2a, ~...Memory section, 10...
System bus, 11... Image bus, 31... Keyboard, 32... Mouse, 130 to 136... Decode circuit, 140... Mapping circuit, 147... Mapping RAM.

Claims (2)

[Claims] (1) The first one has control programs for various functions.
a second storage means storing a conversion address corresponding to the control program stored in the first storage means; and processing means that reads a conversion address according to the control program from the second storage means and converts the address supplied from the control means in accordance with the conversion address. A document processing device characterized by: (2) The document processing device according to claim 1, wherein the various functions include a document filing function, a word processing function, a personal computer function, and the like.