JPS63133672A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63133672A JPS63133672A JP28272286A JP28272286A JPS63133672A JP S63133672 A JPS63133672 A JP S63133672A JP 28272286 A JP28272286 A JP 28272286A JP 28272286 A JP28272286 A JP 28272286A JP S63133672 A JPS63133672 A JP S63133672A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tungsten
- tungsten silicide
- silicon
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- 239000000203 mixture Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にポリサイド電極の構造
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a polycide electrode.
(従来の技術〕
従来、半導体装置のゲート電極、取出電極および内部配
線のコンタクト電極等の各電極材にはアルミニウムまた
は活性化されたポリシリコンなどが用いられて来たが、
半導体装置が微細化され高集積化されるに伴ない最近で
は活性化されたポリシリコン膜とタングステン・シリサ
イド膜からなる2層構造のポリサイド電極が用いられる
ようになった。(Prior Art) Conventionally, aluminum or activated polysilicon has been used for electrode materials such as gate electrodes, extraction electrodes, and internal wiring contact electrodes of semiconductor devices.
As semiconductor devices have become smaller and more highly integrated, polycide electrodes having a two-layer structure consisting of an activated polysilicon film and a tungsten silicide film have recently come into use.
半導体装置に用いられる電極に要求される特性の一つに
、電極自身の電気抵抗の問題がある。一般にこの電気抵
抗は半導体装置の動作速度の面から考えると出来るだけ
低抵抗であることが望ましいが、前述した従来のタング
ステン・シリサイド・ポリサイド構造の電極では未だ充
分に低抵抗化されたとは言い難い。この2層構造のポリ
サイド電極は、通常、シリコン/タングステン組成比が
2.6乃至2.8程度のダンゲステン・シリサイド膜で
形成される。従って、電極としての電気抵抗値を更に下
げるためにはこのタングステン・シリサイド膜中のシリ
コンの割合を少なくすればよいことは明らかである。し
かしながら、シリコン/りングステン組成比が2.6未
満のタングステン・シリサイド膜を用いると電極形成後
の熱処理工程でタングステン・シリサイド膜が下地基板
から!l1ilillする場合があるので信頼性上好ま
しからざる問題を生じる。One of the characteristics required of electrodes used in semiconductor devices is the electrical resistance of the electrodes themselves. Generally speaking, it is desirable for this electrical resistance to be as low as possible in terms of the operating speed of semiconductor devices, but it is difficult to say that the resistance has been sufficiently reduced with the conventional tungsten-silicide-polycide structure electrodes mentioned above. . This two-layer polycide electrode is usually formed of a dungesten silicide film having a silicon/tungsten composition ratio of about 2.6 to 2.8. Therefore, it is clear that in order to further reduce the electrical resistance value of the electrode, the proportion of silicon in this tungsten silicide film should be reduced. However, if a tungsten silicide film with a silicon/ringsten composition ratio of less than 2.6 is used, the tungsten silicide film will be removed from the base substrate during the heat treatment process after electrode formation! This may cause an undesirable problem in terms of reliability.
本発明の目的は、上記の状況に鑑み、下地基板との剥離
現象を生じることなき低電気抵抗のポリサイド電極を備
えた半導体装置を提供することである。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device equipped with a polycide electrode having low electrical resistance without causing a peeling phenomenon from a base substrate.
r問題点を解決するための手段〕
本発明によれば、半導体装置は、不純物ドープのポリシ
リコン膜と前記ポリシリコン膜上に順次積層されるシリ
コン/タングステン組成比がそれぞれ2.6以上および
2.6未満の第1および第2のタングステン・シリサイ
ド膜とからなる3層構造のポリサイド電極を備えて構成
される。Means for Solving Problems] According to the present invention, a semiconductor device has an impurity-doped polysilicon film and a silicon/tungsten composition ratio stacked sequentially on the polysilicon film of 2.6 or more and 2.6 or more, respectively. A polycide electrode having a three-layer structure including a first tungsten silicide film and a second tungsten silicide film having a thickness of less than .6 is provided.
すなわち、本発明によれば、活性化されたボI)シリコ
ン股上にはシリコン/タングステン組成比の互いに異な
る2種のタングステン・シリサイド膜を続けて形成した
3層構造のタングステンシリサイド・ポリサイド構造の
電極が使用される。That is, according to the present invention, an electrode having a three-layer tungsten silicide/polycide structure in which two types of tungsten silicide films having different silicon/tungsten composition ratios are sequentially formed on the activated silicon layer. is used.
本発明はその製造方法を説明することによって良く理解
し得ると考えられるので、以下製造工程図を参照して本
発明の詳細な説明する。Since it is believed that the present invention can be better understood by explaining its manufacturing method, the present invention will be described in detail below with reference to manufacturing process diagrams.
第1図(a)〜(e)は本発明をMO3電界効果トラン
ジスタのゲート電極に実施した場合の製造工程図である
。本実施例の工程図によれば、半導体基板1上には第1
図(a>に示す如くフィールド酸化膜2およびゲート酸
化膜3が通常の技術によりまず形成され、ついで第1図
(b)のようにポリシリコン膜4が例えば膜厚1500
人で形成されると共に通常の熱拡散法による不純物ドー
プと表面ガラス層のエツチング除去が行なわれる。ここ
で、第1図(C>に示すようにシリコン/タングステン
組成比が例えば2.7のタングステン・シリサイド・タ
ーゲットを装着したスパッター装置(図示しない)を用
いて第1タングステン・シリサイド膜がポリシリコン膜
4上に例えば膜厚1500人で形成され、つづいてシリ
コン/タングステン組成比が例えば2.5の第2のタン
グステン・シリサイド・ターゲットを装着したスパッタ
ー装置を(図示しない)を用いて第2のタングステン・
シリサイド膜6が例えば膜厚1500人で第1図(d)
に示すように順次積層形成される。従って、第1および
第2のタングステン・シリサイド膜5および6ならびに
最下層のポリシリコン膜4をフォトエツチング技術によ
り選択除去すれば第1図(e)に示す如き3層構造のポ
リサイドゲート電極7を得ることができる。FIGS. 1(a) to 1(e) are manufacturing process diagrams when the present invention is applied to the gate electrode of an MO3 field effect transistor. According to the process diagram of this embodiment, there is a first layer on the semiconductor substrate 1.
As shown in FIG. 1(a), a field oxide film 2 and a gate oxide film 3 are first formed by a conventional technique, and then a polysilicon film 4 is formed to a thickness of, for example, 1,500 mm as shown in FIG. 1(b).
The glass layer is formed manually, and the impurity doping and etching removal of the surface glass layer are performed by a conventional thermal diffusion method. Here, as shown in FIG. 1 (C>), the first tungsten silicide film is made of polysilicon using a sputtering apparatus (not shown) equipped with a tungsten silicide target having a silicon/tungsten composition ratio of, for example, 2.7. A sputtering device (not shown) equipped with a second tungsten silicide target having a silicon/tungsten composition ratio of, for example, 2.5 is used to form a second tungsten silicide target on the film 4 to a thickness of, for example, 1,500 yen. tungsten·
For example, if the silicide film 6 has a thickness of 1500, as shown in FIG. 1(d).
They are sequentially layered as shown in FIG. Therefore, if the first and second tungsten silicide films 5 and 6 and the lowermost polysilicon film 4 are selectively removed by photoetching, a three-layer polycide gate electrode 7 as shown in FIG. 1(e) is formed. can be obtained.
本実施例によれば、ポリサイド・ゲート電極7は熱処理
工程で剥離し難い膜質をもつシリコン/タングステン組
成比2.6以上のタングステン・シリサイド膜が下層に
、また電気抵抗値の小さな膜質の組成比2.6未満のタ
ングステン・シリサイド膜が上層にして形成されている
ので、両者の利点を共有することができ熱処理に対する
安定性と低電気抵抗特性とを兼備する。すなわち、実験
によれば、ポリシリコン膜4と第1および第2のタング
ステン・シリサイド膜5および6の膜厚比をそれぞれ4
:2:2に設定した場合には、それと同一形状寸法の従
来構造電極に対しそれぞれ20〜30%程度まで電気抵
抗を軽減し得ることが立証される。According to this embodiment, the polycide gate electrode 7 has a tungsten silicide film with a silicon/tungsten composition ratio of 2.6 or more, which has a film quality that is difficult to peel off during a heat treatment process, as an underlying layer, and a film composition ratio with a low electrical resistance value. Since the tungsten silicide film with a particle diameter of less than 2.6 is formed as an upper layer, it can share the advantages of both, and has both stability against heat treatment and low electrical resistance characteristics. That is, according to experiments, the film thickness ratio of the polysilicon film 4 and the first and second tungsten silicide films 5 and 6 was set to 4, respectively.
:2:2, it is proven that the electrical resistance can be reduced by about 20 to 30% compared to the conventional structure electrode of the same shape and size.
第2図(a)〜(C)は本発明をMO3電界効果トラン
ジスタのゲート配線接続およびソース。FIGS. 2(a) to 2(c) show the gate wiring connection and source of an MO3 field effect transistor according to the present invention.
トレイン領域からの取出電極に実施した場合の製造工程
図を示すものである。本実施例によれば、前実施例同様
半導体基板11上にフィールド酸化1摸12、ゲート酸
化膜13がまず形成され、更に、ゲート電極14、ソー
ス、ドレイン拡散層15.16、層間パッシベーション
膜17、コンタクト孔18がそれぞれ形成される。〔第
2図(a>参照〕。ついで前実施例で詳述したように、
不純物をドープされたポリシリコン膜1つ、第1のタン
グステン・シリサイド膜20および第2のタングステン
・シリサイド膜21がそれぞれ形成される。〔第2図(
b)参照〕。第1および第2のタングステン・シリサイ
ド膜20および21ならびにポリシリコン膜19をフォ
トエツチング技術により遷択除去すれば第2図(c)に
示すようにゲート電極14およびソース、ドレイン領域
15.16上に配線用ポリサイド電極22および23.
24をそれぞれ形成し得る。本実施例の配線用ポリサイ
ド電極はタングステン・シリサイド膜が組成比を異にす
る2つの膜質の積層膜から形成されているので、熱処理
に対する安定性と低電気抵抗特性とをそれぞれ兼備する
。This is a diagram showing a manufacturing process when the electrode is taken out from the train region. According to this embodiment, as in the previous embodiment, a field oxide film 12 and a gate oxide film 13 are first formed on a semiconductor substrate 11, and then a gate electrode 14, source and drain diffusion layers 15 and 16, and an interlayer passivation film 17 are formed. , contact holes 18 are formed, respectively. [See Figure 2 (a>)] Then, as detailed in the previous example,
One impurity-doped polysilicon film, a first tungsten silicide film 20, and a second tungsten silicide film 21 are formed, respectively. [Figure 2 (
b) see]. If the first and second tungsten silicide films 20 and 21 and the polysilicon film 19 are selectively removed by photoetching, the gate electrode 14 and the source and drain regions 15 and 16 will be etched as shown in FIG. 2(c). Polycide electrodes for wiring 22 and 23.
24 respectively. Since the wiring polycide electrode of this embodiment is formed from a laminated film of two tungsten silicide films having different composition ratios, it has both stability against heat treatment and low electrical resistance characteristics.
以上詳細に説明したように、本発明によれば、半導体装
置におけるタングステン・シリサイド・ポリサイドi造
の電極は耐熱処理性と低抵抗特性のそれぞれ異なる性質
をもつ2つのタングステン・シリサイド膜の積層膜を含
んで3層構造に形成されているので、電極の電気抵抗を
少くとも20〜30%程度軽減し得ると共に下地基板と
の剥離現象を防止し得る効果があり、半導体装置の信頼
性を著しく向上せしめることができる。As explained in detail above, according to the present invention, an electrode made of tungsten silicide polycide in a semiconductor device is made of a laminated film of two tungsten silicide films each having different properties such as heat treatment resistance and low resistance characteristics. Since the electrode is formed in a three-layer structure, it has the effect of reducing the electrical resistance of the electrode by at least 20 to 30% and preventing peeling from the underlying substrate, significantly improving the reliability of semiconductor devices. You can force it.
第1図(a)〜(e)は本発明をMO3電界効果トラン
ジスタのゲーT〜電極に実施した場合の製造工程図、第
2図(a)〜(c)は本発明をMO8電界効果トランジ
スタのゲート配線接続およびソース、ドレイン領域から
の取出電極に実施した場合の製造工程図である。
1.11・・・半導体基板、2.]2・・・フィールド
酸化膜、3.13・・・デー1〜酸化膜、4,1つ・・
・不純物を含むポリシリコン膜、5.20・・・第1の
タングステン・シリサイド膜、6,21・・・第2のタ
ングステン・シリサイド膜、7・・・(本発明にかかる
)3層構造のポリサイド・ゲート電極、22゜23.2
4・・・(本発明にかかる)3層構造の配線用ポリサイ
ド電極。
代理人 弁理士 内 原 音(オ慰
又−で
(久)
(b)
(C)
第1図
(d)
第f区
メツ4間パッシベーションガ丈 /2コンタクト孔((
:;I−)
茅2図
(C)
第2図Figures 1 (a) to (e) are manufacturing process diagrams in which the present invention is applied to the gate electrodes of MO3 field effect transistors, and Figures 2 (a) to (c) are manufacturing process diagrams in which the present invention is applied to the gate electrodes of MO8 field effect transistors. FIG. 3 is a manufacturing process diagram when the gate wiring connection and the lead-out electrodes from the source and drain regions are performed. 1.11... semiconductor substrate, 2. ]2...Field oxide film, 3.13...Day 1 ~ Oxide film, 4, one...
・Polysilicon film containing impurities, 5.20...first tungsten silicide film, 6,21...second tungsten silicide film, 7...3-layer structure (according to the present invention) Polycide gate electrode, 22°23.2
4... (according to the present invention) polycide electrode for wiring with a three-layer structure. Agent Patent Attorney Uchihara Oto (Okonomata-de (ku) (b) (C) Figure 1 (d) Section f 4-space passivation length /2 contact hole ((
:;I-) Kaya Figure 2 (C) Figure 2
Claims (1)
上に順次積層されるシリコン/タングステン組成比がそ
れぞれ2.6以上および2.6未満の第1および第2の
タングステン・シリサイド膜とからなる3層構造のポリ
サイド電極を備えることを特徴とする半導体装置。A three-layer structure consisting of an impurity-doped polysilicon film and first and second tungsten silicide films having a silicon/tungsten composition ratio of 2.6 or more and less than 2.6, which are sequentially laminated on the polysilicon film. A semiconductor device comprising a polycide electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28272286A JPS63133672A (en) | 1986-11-26 | 1986-11-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28272286A JPS63133672A (en) | 1986-11-26 | 1986-11-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63133672A true JPS63133672A (en) | 1988-06-06 |
Family
ID=17656190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28272286A Pending JPS63133672A (en) | 1986-11-26 | 1986-11-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63133672A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0462845A (en) * | 1990-06-25 | 1992-02-27 | Matsushita Electron Corp | Manufacture of laminated interconnection |
JPH0479330A (en) * | 1990-07-23 | 1992-03-12 | Matsushita Electron Corp | Method of forming laminated wiring |
US6103606A (en) * | 1996-09-21 | 2000-08-15 | United Microelectronics Corp. | Method of fabricating a word line |
US6188119B1 (en) * | 1997-02-10 | 2001-02-13 | Nec Corporation | Semiconductor device having barrier metal layer between a silicon electrode and metal electrode and manufacturing method for same |
GB2319658B (en) * | 1996-09-21 | 2001-08-22 | United Microelectronics Corp | Method of fabricating a word line |
US6894365B2 (en) * | 1998-11-09 | 2005-05-17 | Ricoh Company, Ltd. | Semiconductor device having an integral resistance element |
KR100650759B1 (en) | 2005-06-30 | 2006-11-27 | 주식회사 하이닉스반도체 | Tungsten Silicide Thin Film Formation Method |
-
1986
- 1986-11-26 JP JP28272286A patent/JPS63133672A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0462845A (en) * | 1990-06-25 | 1992-02-27 | Matsushita Electron Corp | Manufacture of laminated interconnection |
JPH0479330A (en) * | 1990-07-23 | 1992-03-12 | Matsushita Electron Corp | Method of forming laminated wiring |
US6103606A (en) * | 1996-09-21 | 2000-08-15 | United Microelectronics Corp. | Method of fabricating a word line |
GB2319658B (en) * | 1996-09-21 | 2001-08-22 | United Microelectronics Corp | Method of fabricating a word line |
US6188119B1 (en) * | 1997-02-10 | 2001-02-13 | Nec Corporation | Semiconductor device having barrier metal layer between a silicon electrode and metal electrode and manufacturing method for same |
US6894365B2 (en) * | 1998-11-09 | 2005-05-17 | Ricoh Company, Ltd. | Semiconductor device having an integral resistance element |
US7151038B2 (en) | 1998-11-09 | 2006-12-19 | Ricoh Company, Ltd. | Semiconductor device having an integral resistance element |
KR100650759B1 (en) | 2005-06-30 | 2006-11-27 | 주식회사 하이닉스반도체 | Tungsten Silicide Thin Film Formation Method |
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