JPS63129633A - Surface treatment for semiconductor - Google Patents
Surface treatment for semiconductorInfo
- Publication number
- JPS63129633A JPS63129633A JP27531586A JP27531586A JPS63129633A JP S63129633 A JPS63129633 A JP S63129633A JP 27531586 A JP27531586 A JP 27531586A JP 27531586 A JP27531586 A JP 27531586A JP S63129633 A JPS63129633 A JP S63129633A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- semiconductor
- film
- defects
- contamination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000004381 surface treatment Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 30
- 230000007547 defect Effects 0.000 description 12
- 238000011109 contamination Methods 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 230000002411 adverse Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 231100000989 no adverse effect Toxicity 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Weting (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
本発明は、半導体表面処理方法に於いて、所要の工程に
入る前、Ｓｉ半導体ウェハに０３を吹き付けて５１０２
Ｍを成長させ、その５ｉ０２膜を除去することに依り、
Ｓｉ半導体ウェハの汚染や欠陥を取り除き、また、その
除去プロセスがＳｉ半導体ウェハに悪影響を与えないよ
うにしたものである。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention provides a semiconductor surface treatment method in which a Si semiconductor wafer is sprayed with 5102 03 before entering a required step.
By growing M and removing the 5i02 film,
This method removes contamination and defects from the Si semiconductor wafer, and prevents the removal process from having an adverse effect on the Si semiconductor wafer.
本発明は、高性能の半導体装置を製造する際に適用して
有効な半導体表面処理方法に関する。The present invention relates to a semiconductor surface treatment method that is effective when applied to manufacturing high-performance semiconductor devices.
一般に、半導体装置の製造工程に於いて、半導体ウェハ
の表面が汚染されたり、或いは、欠陥を生じたりするこ
とは多いが、成るプロセスを開始する前に、そのような
汚染や欠陥を積極的に除去することは殆ど行われず、せ
いぜい、自然酸化膜を例えばフン酸系エツチング液で除
去するぐらいの前処理をしている程度である。In general, during the manufacturing process of semiconductor devices, the surface of the semiconductor wafer is often contaminated or defects occur, but such contamination and defects are actively removed before the manufacturing process begins. Removal is hardly performed, and at most, the natural oxide film is pretreated to be removed using, for example, a hydrochloric acid etching solution.
近年の半導体装置は、微細化、高集積化が著しく進んで
いるので、前記したような汚染或いは欠陥が製造歩留り
や性能に大きな影響を与えるようになってきた。In recent years, semiconductor devices have become significantly smaller and more highly integrated, so that the above-mentioned contamination or defects have come to have a significant impact on manufacturing yield and performance.
通常、そのような汚染は勿論のこと、欠陥も半導体ウェ
ハの表面に多く発生しているので、それ等を除去するに
は、何らかの方法で半導体ウェハの表面をとってしまう
と良い。Generally, not only such contamination but also many defects occur on the surface of a semiconductor wafer, so in order to remove such contamination, it is preferable to remove the surface of the semiconductor wafer by some method.
然しなから、そのような加工が半導体ウェハに作り込ま
れた諸構成にダメージを与えるものであってはならない
。However, such processing must not damage the structures built into the semiconductor wafer.
本発明は、半導体ウェハの表面を、他に悪影響を与える
ことなく、必要とされる充分な厚さだけ容易に除去でき
るようにし、汚染や欠陥の問題を解消しようとする。The present invention seeks to eliminate the problem of contamination and defects by allowing the surface of a semiconductor wafer to be easily removed to the required sufficient thickness without adversely affecting others.
本発明では、半導体ウェハの表面を酸化して汚染や欠陥
を酸化膜中に取り込み、その酸化膜を除去することで汚
染や欠陥の解消を図っているのであるが、ここで汚染の
みでなく表面欠陥まで除去しようとすると、それに必要
とされる酸化膜の厚さは約１００〔人〕程度にもなるの
で、これを熱酸化或いはプラズマ酸化などの技術を適用
して形成したのでは、当然、半導体ウェハに作り込まれ
た部分に悪影響を与えることになる。因に、従来行われ
ている前処理に於いては、数〔人〕〜数十〔人〕程度の
自然酸化膜を除去しているに過ぎない（ここで「数」は
「２〜３」を意味する）。In the present invention, the surface of the semiconductor wafer is oxidized to incorporate contamination and defects into the oxide film, and the oxide film is removed to eliminate the contamination and defects. If you try to remove even the defects, the thickness of the oxide film required is about 100 [people], so it is natural that this would be formed using techniques such as thermal oxidation or plasma oxidation. This will have an adverse effect on the parts built into the semiconductor wafer. Incidentally, in conventional pretreatment, only a few to several dozen natural oxide films are removed (here, the number is 2 to 3). ).
そこで、本発明に依る半導体表面処理方法に於いては、
加熱したＳｉ半導体ウェハ（例えばＳｉ半導体ウェハ８
）に０３を吹き付けて５ｉ０２膜を形成する工程と、次
いで、エツチング液（例えばフン酸（５〔％〕）系エツ
チング液）中に浸漬して該Ｓｉｏ２膜を除去する工程と
が含まれている。Therefore, in the semiconductor surface treatment method according to the present invention,
A heated Si semiconductor wafer (e.g. Si semiconductor wafer 8
) to form a 5i02 film, and then a step of removing the Sio2 film by immersing it in an etching solution (for example, a hydrochloric acid (5%) based etching solution). .
前記手段を採ることに依り、Ｓｉ半導体ウェハの汚染や
表面欠陥を容易に除去することができ、そして、０３を
吹き付けてＳ ｉ ０２膜を形成していることから、そ
のプロセスは通常の熱酸化などに比較すると這かに低温
であって、その除去プロセスがＳｉ半導体ウェハに悪影
響を与えることは皆無であり、従って、そのＳｉ半導体
ウェハを用いて製造した半導体装置の特性は向上する。By adopting the above method, contamination and surface defects on the Si semiconductor wafer can be easily removed, and since the Si 02 film is formed by spraying 03, the process is similar to ordinary thermal oxidation. The removal process has no adverse effect on the Si semiconductor wafer, and therefore the characteristics of semiconductor devices manufactured using the Si semiconductor wafer are improved.
図は本発明を実施する装置の一例を表す要部説明図であ
る。The figure is an explanatory diagram of main parts of an example of an apparatus for carrying out the present invention.
図に於いて、１は反応室、２は送気管、３は排気管、４
はサセプタ、５はヒータ、６はガス拡散板、７はオゾナ
イザ、８はＳｉ半導体ウェハをそれぞれ示している。尚
、ガス拡散板６はガスがウェハ表面に均一に流れるよう
にする為のものである。In the figure, 1 is the reaction chamber, 2 is the air pipe, 3 is the exhaust pipe, and 4 is the reaction chamber.
5 is a susceptor, 5 is a heater, 6 is a gas diffusion plate, 7 is an ozonizer, and 8 is a Si semiconductor wafer. Note that the gas diffusion plate 6 is provided to allow gas to flow uniformly over the wafer surface.
図示の装置を用いて本発明を実施するには、サセプタ４
上に載置されたＳｉ半導体ウェハ８をヒータ５で加熱し
ておき、送気管２からオゾナイザ７に０２を送入すると
、オゾナイザ７から反応室１に０２＋０３の混合ガスが
吹き込まれ、Ｓｉ半導体ウェハ８にＳ ｉ Ｏ２膜が形
成される。尚、この場合、Ｓｉ半導体ウェハ８の温度は
、約２００〜３００（’Ｃ）程度の範囲で適宜に選択す
れば良く、この程度の温度では、Ｓｉ半導体ウェハ８に
不純物拡散領域などが形成されている場合であっても、
加熱の影響を受けることはない。To practice the invention using the illustrated apparatus, a susceptor 4
The Si semiconductor wafer 8 placed on top is heated by the heater 5, and when 02 is fed into the ozonizer 7 from the air pipe 2, a mixed gas of 02+03 is blown into the reaction chamber 1 from the ozonizer 7, and the Si semiconductor wafer is heated. 8, a SiO2 film is formed. In this case, the temperature of the Si semiconductor wafer 8 may be appropriately selected within the range of approximately 200 to 300 ('C); at this temperature, impurity diffusion regions and the like are not formed in the Si semiconductor wafer 8. Even if
It is not affected by heating.
このようにして５ｉ０２膜を形成した場合の主要データ
を例示すると次の通りである。An example of the main data when forming the 5i02 film in this way is as follows.
Ｓｉ半導体ウェハ８の温度＝２５０（’Ｃ）ｏ２＋ｏ３
の流量：２ＳＬＭ（標準状態で１ 〔分〕当たり２（Ｊ
！：１）
０３の濃度：約５〔％〕程度
圧カニｌ（ａｔｍ）
反応時間：１０〔分〕
５ｔｏ２膜厚さ：１００（人〕
この後、フッ酸（５〔％〕）系エツチング液に浸漬して
時間３０〔秒〕のウェット・エツチングを行って５１０
２膜を除去する。Temperature of Si semiconductor wafer 8 = 250 ('C) o2 + o3
Flow rate: 2 SLM (2 (J per minute) under standard conditions)
! :1) Concentration of 03: Approximately 5 [%] Pressure l (ATM) Reaction time: 10 [minutes] 5to2 film thickness: 100 (people) After this, use hydrofluoric acid (5 [%]) based etching solution. 510 by dipping and wet etching for 30 seconds.
2 Remove the film.
前記説明した本発明に依る処理を行ったＳｉ半導体ウェ
ハと行わないＳｉ半導体ウェハを用いてＭＯＳダイオー
ドを形成して比較したところ、本発明に依る処理を経た
Ｓｉ半導体ウェハに形成されたＭＯＳダイオードでは少
数キャリヤのライフ・タイムが２０ 〔％〕も向上した
。When MOS diodes were formed and compared using Si semiconductor wafers that were processed according to the present invention described above and Si semiconductor wafers that were not processed, it was found that MOS diodes formed on Si semiconductor wafers that were processed according to the present invention Minority carrier life time improved by 20%.
これは、本発明に依る処理を行ったＳｉ半導体ウェハで
は、汚染や欠陥が除去され、また、その除去プロセスが
何らの悪影響も与えていないことを示すものと考えられ
る。This is considered to indicate that contamination and defects are removed from the Si semiconductor wafers treated according to the present invention, and that the removal process does not have any adverse effects.
本発明に依る半導体表面処理方法に於いては、所要の工
程に入る前、Ｓｉ半導体ウェハに０３を吹き付けて５ｉ
０２膜を成長させ、そのＳ ｉ Ｏｚ膜を除去するよう
にしている。In the semiconductor surface treatment method according to the present invention, before starting the required process, the Si semiconductor wafer is sprayed with 03 and 5i
02 film is grown, and the SiOz film is removed.
このような構成を採ることに依り、Ｓｉ半導体ウェハの
汚染や表面欠陥を容易に除去することができ、そして、
０３を吹き付けて５ｉ０２膜を形成していることから、
そのプロセスは通常の熱酸化などに比較すると蟲かに低
温であって、その除去プロセスがＳｉ半導体ウェハに悪
影響を与えることは皆無であり、従って、そのＳｉ半導
体ウェハに作り込まれた半導体装置の特性は向上する。By adopting such a configuration, contamination and surface defects on the Si semiconductor wafer can be easily removed, and
Since the 5i02 film is formed by spraying 03,
The process is extremely low-temperature compared to normal thermal oxidation, and the removal process has no adverse effect on the Si semiconductor wafer. Characteristics will improve.
図は本発明を実施する装置の一例を表す要部説明図であ
る。
図に於いて、１は反応室、２は送気管、３は排気管、４
はサセプタ、５はヒータ、６はガス拡散板、７はオゾナ
イザ、８はＳｉ半導体ウェハをそれぞれ示している。The figure is an explanatory diagram of main parts of an example of an apparatus for carrying out the present invention. In the figure, 1 is the reaction chamber, 2 is the air pipe, 3 is the exhaust pipe, and 4 is the reaction chamber.
5 is a susceptor, 5 is a heater, 6 is a gas diffusion plate, 7 is an ozonizer, and 8 is a Si semiconductor wafer.
Claims (1)
Ｏ＿２膜を形成する工程と、 次いで、エッチング液中に浸漬して該ＳｉＯ＿２膜を除
去する工程と が含まれてなることを特徴とする半導体表面処理方法。[Claims] O_3 is sprayed onto a heated Si semiconductor wafer.
A semiconductor surface treatment method comprising: forming an O_2 film; and then removing the SiO_2 film by immersing it in an etching solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27531586A JPS63129633A (en) | 1986-11-20 | 1986-11-20 | Surface treatment for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27531586A JPS63129633A (en) | 1986-11-20 | 1986-11-20 | Surface treatment for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63129633A true JPS63129633A (en) | 1988-06-02 |
Family
ID=17553731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27531586A Pending JPS63129633A (en) | 1986-11-20 | 1986-11-20 | Surface treatment for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63129633A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5028560A (en) * | 1988-06-21 | 1991-07-02 | Mitsubishi Denki Kabushiki Kaisha | Method for forming a thin layer on a semiconductor substrate |
| US5178682A (en) * | 1988-06-21 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Method for forming a thin layer on a semiconductor substrate and apparatus therefor |
| US5762755A (en) * | 1991-05-21 | 1998-06-09 | Genus, Inc. | Organic preclean for improving vapor phase wafer etch uniformity |
| WO2000042644A1 (en) * | 1999-01-12 | 2000-07-20 | Sumitomo Sitix Silicon Inc. | System and method for surface passivation |
| WO2005114716A3 (en) * | 2004-05-07 | 2006-02-09 | Memc Electronic Materials | Process for metallic contamination reduction in silicon wafers |
| JP2006108243A (en) * | 2004-10-01 | 2006-04-20 | Fuji Electric Holdings Co Ltd | Method for manufacturing semiconductor device |
| US7063992B2 (en) | 2003-08-08 | 2006-06-20 | Solid State Measurements, Inc. | Semiconductor substrate surface preparation using high temperature convection heating |
-
1986
- 1986-11-20 JP JP27531586A patent/JPS63129633A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5028560A (en) * | 1988-06-21 | 1991-07-02 | Mitsubishi Denki Kabushiki Kaisha | Method for forming a thin layer on a semiconductor substrate |
| US5178682A (en) * | 1988-06-21 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Method for forming a thin layer on a semiconductor substrate and apparatus therefor |
| US5762755A (en) * | 1991-05-21 | 1998-06-09 | Genus, Inc. | Organic preclean for improving vapor phase wafer etch uniformity |
| WO2000042644A1 (en) * | 1999-01-12 | 2000-07-20 | Sumitomo Sitix Silicon Inc. | System and method for surface passivation |
| US6511921B1 (en) | 1999-01-12 | 2003-01-28 | Sumco Phoenix Corporation | Methods for reducing the reactivity of a semiconductor substrate surface and for evaluating electrical properties of a semiconductor substrate |
| US7063992B2 (en) | 2003-08-08 | 2006-06-20 | Solid State Measurements, Inc. | Semiconductor substrate surface preparation using high temperature convection heating |
| WO2005114716A3 (en) * | 2004-05-07 | 2006-02-09 | Memc Electronic Materials | Process for metallic contamination reduction in silicon wafers |
| US7084048B2 (en) | 2004-05-07 | 2006-08-01 | Memc Electronic Materials, Inc. | Process for metallic contamination reduction in silicon wafers |
| CN100466200C (en) * | 2004-05-07 | 2009-03-04 | Memc电子材料有限公司 | Process for metallic contamination reduction in silicon wafers |
| JP2006108243A (en) * | 2004-10-01 | 2006-04-20 | Fuji Electric Holdings Co Ltd | Method for manufacturing semiconductor device |
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