JPS63128665A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To obtain good photoelectric conversion characteristics and afterimage characteristics without augmenting the size of photoelectric conversion cells by a method wherein a region consisting of a one conductivity type semiconductor for forming a control electrode region and a region, which is provided under the region of an inverse conductivity type semiconductor and consists of a one conductivity type semiconductor, are used as main electrode regions and a transistor, which is controlled by an insulating gate electrode, is formed in a longitudinal direction. CONSTITUTION:An n<+> buried layer 202 and an n<-> collector region 203 are formed on a p-type Si substrate 201. The bipolar transistor of each cell is constituted of a p<-> base region 207 on the n<-> collector region 203 and an n<+> emitter region 208 and a p<+> region 209 to be junctioned to the p<-> base region 207 opposes to a capacitor electrode 206 holding an oxide film 205 between them and constitutes a capacitor Cox for controlling the potential of the p<-> base region 207. Moreover, the n<+> buried layer 202 is not formed in the lower direction of the p<+> region 209, the p<+> region 209 and the p-type substrate 201 are formed at a distance of about 4-5 mum and the source and drain regions of a transistor Qt for refresh are constituted.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a photoelectric conversion device that accumulates carriers excited by light in a control electrode region of a transistor, and particularly relates to a photoelectric conversion device that accumulates carriers excited by light in a control electrode region of a transistor. The present invention relates to a photoelectric conversion device having a switch means for setting a value.

[Prior Art] FIG. 7(A) is shown in Japanese Patent Application No. 58-120755, in which photoelectric conversion cells are arranged on an n-silicon substrate 101, and each cell is made of Si02.

It is electrically insulated from adjacent cells by an element isolation region 102 made of Si3N4, polysilicon, or the like.

Each cell has the following configuration.

Low impurity concentration n formed by epitaxial technology etc.
A P base region 104 and a P region 105 are formed on the - region 103 by doping with a p-type impurity (for example, poron, etc.), and an n+ emitter region 106 is formed in the p base region 104.

The p base region 104 and the p region 105 also serve as the source and drain of a p channel MO5) transistor to be described later.

Oxide 179107 is formed on the n-region 103 in which each region is formed in this way, and the MO
3) A transistor gate electrode 108 and a capacitor electrode 109 are formed.

Capacitor electrode 109 faces p base region 104 with oxide film 107 in between, and constitutes a capacitor for controlling base potential.

In addition, an emitter electrode 110 connected to the n+ emitter region 106. An electrode lll connected to the P region 105 and a collector electrode 112 are formed on the back surface of the substrate 101 with an ohmic contact layer in between.

Next, the operation of the photoelectric conversion cell will be explained.

Light enters from the p base region 104 side, and carriers (holes in this case) corresponding to the amount of light are iaed into the p base ill 04 (accumulation ta!! 21 work).

The base potential changes due to the accumulated carriers, and by reading out the potential change from the emitter electrode 110, an electric signal corresponding to the amount of incident light can be obtained (reading operation).

Next, a refresh operation for removing holes accumulated in p base region 104 will be described.

FIGS. 8(A) and 8(B) are voltage waveform diagrams for explaining the refresh operation.

As shown in FIG. 2A, the MOS transistor is turned on only when a negative voltage equal to or higher than a threshold value is applied to the gate electrode 108.

In the same figure (B), in order to perform a refresh operation, the emitter electrode 110 is grounded, and the electrode ill is set to the ground potential. First, a negative voltage is applied to the gate electrode 108, and the p-channel MO3) transistor is ON
let As a result, the potential of the P base region 104 is
It is a constant value regardless of the level of the accumulated potential. Next, M.O.
After turning off the S transistor, the capacitor electrode 10
By applying a positive refresh voltage pulse to p
Base region 104 is forward biased with respect to n+ emitter region 106, and accumulated holes are removed through grounded emitter electrode 110. Then, when the refresh pulse applied to capacitor electrode 109 falls, p base region 104 returns to the initial state of negative potential (refresh operation).

In this way, after the potential of the p base region 104 is set to a constant potential by the MOS transistor, a new accumulation operation is started without depending on the previous accumulation voltage in order to erase the residual charge by applying a refresh pulse. The photoelectric conversion characteristics and the afterimage characteristics can be improved. In addition, residual charges can be quickly eliminated,
High-speed operation is possible.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional photoelectric conversion device, the problem as shown in FIG.
As shown in A), since the refresh transistor is formed on the light-receiving surface, the cell size increases accordingly.
In particular, this has been a problem in achieving high integration and high resolution when configuring an area sensor.

The present invention is intended to solve the above-mentioned conventional problems, and its purpose is to provide a photoelectric conversion device that can obtain good photoelectric conversion characteristics and afterimage characteristics without increasing the cell size.

[Means for Solving the Problems] A photoelectric conversion device according to the present invention includes: a first region made of a semiconductor of one conductivity type for forming a control electrode region; and a first region arranged to sandwich the first region above and below, respectively. second and third semiconductors of opposite conductivity type to form a main electrode region
a fourth region formed under the third region and made of a semiconductor of one conductivity type; and a semiconductor transistor configured to use the first region and the fourth region as main electrode regions. and an insulated gate electrode that controls the region No. 3.

[Operation] With this configuration, it is possible to form a transistor in the vertical direction in which the first region and the fourth region are used as main electrode regions and are controlled by an insulated gate electrode,
The size of the photoelectric conversion device can be miniaturized.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic sectional view of a first embodiment of a photoelectric conversion device according to the present invention.

In the figure, an n+ buried layer 202 and an n- collector region 203 are formed on a p-type silicon substrate 201, and each cell is electrically isolated from adjacent cells by an element isolation region 204.

The element isolation region 204 is composed of an oxide film 205 and a capacitor electrode 206 made of polysilicon. As an example of a method for forming this element isolation region 204, first, an n buried layer 202 and a collector region 2 are formed on a p substrate 201.
After epitaxially growing the n-region that becomes 0ff,
A groove is formed by anisotropic etching or the like in a portion where the element isolation region 204 is to be formed. After forming an oxide film 205 in the trench by thermal oxidation, a capacitor electrode 206 is formed by filling polysilicon.

The bipolar transistor of each cell has a p base region 207 on an n- collector region 203 and an n+ emitter region 2.
08.

A p medium region 209 is joined to the p base region 207, and the p medium region 209 is connected to the capacitor core 20 with an oxide film 205 in between.
6 and constitutes a capacitor Cox for controlling the potential of the P base region 207.

Further, the n0 buried layer 202 is not formed below the p'' region 209, and the p middle region 209 and the p substrate 201 are formed at a distance of about 4 to 5 pm.

This constitutes the source/drain region of the refresh transistor Qt. The gate electrode of the transistor Qt is
Capacitor electrode 206 formed across oxide film 205
It is.

Further, an n-medium region 210 is connected to the n-collector region 203, and a collector electrode 21O' (not shown) is connected to the n-medium region 210.

An oxide film 211 is formed on the surface of each cell, and an emitter electrode 212 is connected to the n+ emitter region 208. Furthermore, an electrode 213 is formed on the back surface of the p-substrate 201 via an ohmic contact layer.

In this way, since the refresh transistor Qt is formed vertically with respect to the light-receiving surface, an increase in cell size can be avoided.

Further, since each cell is separated by the element isolation region 204 and the n collector region 203 is formed on the p substrate 201, the element isolation effect can be improved.

Furthermore, even if strong light is incident, excess carriers accumulated in the p-base region 207 are removed through the p-substrate 201, preventing them from flowing into adjacent cells and preventing smearing and pluming. Become.

FIG. 2 is a schematic cross-sectional view of a second embodiment of the invention.

Although it has almost the same configuration as the first embodiment.

The upper part of capacitor electrode 206 extends over p base region 207 to increase capacitance.

FIG. 3 is an equivalent circuit diagram of the cell in the above embodiment.

The basic operation of the above embodiment is the same as that of the conventional example.

First, a positive voltage is applied to the collector electrode 210'.

A constant voltage is applied to the electrode 213, and a ground voltage is applied to the capacitor electrode 206, so that the transistor Qt
is turned off, and the p base region 207 is placed in a floating state. Then, carriers corresponding to the illuminance of the incident light are accumulated in this p base region 207 (accumulation operation).

Subsequently, a read pulse of a positive voltage is applied to the capacitor electrode 206 with the emitter electrode 212 in a floating state. At this time, the transistor Qt is OFF because it is a p-channel.
The condition remains. By applying the read pulse, the potential of the p base region 207 increases via the capacitor Cox, and the accumulated voltage is read out to the floating emitter side (read operation).

Next, in order to eliminate the carriers accumulated in the p base region 207, a negative voltage pulse is first applied to the capacitor electrode 206 to turn on the refresh transistor Qt. As a result, the p base region 207 is able to operate on the electrode 2 regardless of the level of the MMr voltage due to the intensity of the illuminance of the incident light.
It is set to a constant voltage applied to 13. continue,
By applying a positive voltage refresh pulse to the capacitor electrode 206 and grounding the emitter electrode 212, carriers remaining in the p base region 207 are removed to the grounded emitter side (refresh operation).

In this way, the p base region 207 returns to its initial state, and the storage, read, and refresh operations are returned to green in the same manner.

FIG. 4 is a circuit diagram of an embodiment of an area sensor using the photoelectric conversion cell described above.

In this embodiment, the photoelectric conversion cells S are arranged in mXn areas.

A constant positive voltage Vcc is applied to each collector electrode 210' of the photoelectric conversion cell S, and a constant voltage Vr is applied to each electrode 213.
c is applied.

The capacitor electrodes 206 of each cell S are commonly connected row by row, and pulses φ1 to φm are applied for performing a read operation and a refresh operation, respectively. Further, each emitter electrode 212 is connected to the vertical lines L1 to Ln for each column, and the vertical lines L1 to Ln are connected to the storage capacitors 01 to Cn, respectively.

Further, capacitors 01 to Cn are transistors Q1 to Q1, respectively.
It is connected to the output line 301 via Qn. The gate electrodes of the transistors Q1 to Qn are respectively connected to parallel output terminals of the scanning circuit 302, and pulses φh1 to φhn are sequentially outputted from the parallel output terminals.

The output line 301 is grounded via a refresh transistor Qrh, and a pulse φr2 is applied to the gate electrode of the transistor Qrh. Further, the output line 301 is connected to the input terminal of the output amplifier 303,
An output signal Vout is output from the output terminal of the output amplifier 303 to the outside.

Further, the vertical lines L1 to Ln are each connected to a transistor Qr1.
~Qrn to ground. Further, a pulse φrl is applied to the gate electrode of each transistor.

FIG. 5 is a timing chart for explaining the operation of the area sensor.

First, it is assumed that a certain period of time has elapsed since the cells Sll to 31n in the first row started the storage operation.

In the figure, a low-level pulse φr1 turns off the transistors Qrx to Q r n and puts the vertical line L1xLn in a floating state. Subsequently, a read pulse is applied to the capacitor electrode 206 in the first row using a high-level pulse φ1, whereby the read signal of the cells 311 to 31n in the first row is applied to the capacitors C1 to Cn.
is accumulated in Subsequently, a pulse φh is sent from the scanning circuit 302.
1 to φhn are output, the transistors Q1 to Qn are sequentially turned on, and the read signals of the first row stored in the capacitors 01 to Cn are sequentially taken out to the output line 301.
It is output from the output lamp 303 to the outside. However, each time the signal is output to the outside, the transistor Qrh is turned on by the pulse φr2, and the residual charge on the output line 301 is cleared.

When all the read signals of the first row are output, the pulse φr
1 turns on the transistors Qr1 to Qrn, and the vertical line L1''Ln is grounded, thereby grounding the emitter electrode 212 of each cell and clearing the residual charges in the capacitors 01 to Cn.

Then, a negative voltage is first applied to the capacitor electrode 206 by the pulse φ1, and the base potentials of the cells SL1 to 31n in the first row are set to a constant potential Vrc regardless of the accumulated voltage. Subsequently, a positive voltage refresh pulse is applied to the capacitor electrode 206 to eliminate carriers in the base as described above.

After the read and refresh operations are completed,
Cells 511 to S1n in the if row start an accumulation operation.

At the same time, the cells 521 to S2n in the second row perform a read operation by the pulse φ2, and after the subsequent output operation of the read signal, perform a similar refresh operation and start the Mm operation.

Similarly, the same operation is sequentially repeated from the third row to the m-th row using the pulses φ3 to φm, and the read signals of all the cells are serially output from the output amplifier 303 to the outside. Moreover, in each row, in order to perform a refresh operation and start an accumulation operation after outputting a read signal to the outside, M
The tit time is the same for each row.

FIG. 6 is a schematic configuration diagram of an example of an imaging device using the above photoelectric conversion device.

In the figure, an image sensor 401 corresponds to the photoelectric conversion device shown in FIG. The output signal Vout of the image sensor 401 is subjected to processing such as gain adjustment by the signal processing circuit 402, and is output as a standard television signal such as an NTSC signal.

Further, each of the above pulses for driving the image sensor 401 is supplied by a driver 403, and the driver 403 operates under the control of a control unit 404. In addition, the control unit 40
4 is a signal processing circuit 402 based on the output of the image sensor 401.
At the same time, the exposure control means 405 is controlled to adjust the amount of light incident on the image sensor 401.

As described above, in this embodiment, good photoelectric conversion characteristics and afterimage characteristics can be obtained without increasing the cell size, so that a high resolution image sensor 401 can be constructed and a high quality image signal without afterimages can be obtained. be able to.

[Effects of the Invention] As described above in detail, the photoelectric conversion device according to the present invention has the first region and the fourth region as main electrode regions, and transistors controlled by insulated gate electrodes are formed in the vertical direction. Thus, the above-mentioned good photoelectric conversion characteristics and afterimage characteristics can be obtained without increasing the size of the photoelectric conversion cell.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a first embodiment of a photoelectric conversion device according to the present invention. FIG. 2 is a schematic sectional view of a second embodiment of the present invention, FIG. 3 is an equivalent circuit diagram of a cell in the above embodiment, and FIG. 4 is an implementation of an area sensor using the above photoelectric conversion cell. Example schematic. FIG. 5 is a timing chart for explaining the operation of the area sensor, FIG. 6 is a schematic configuration diagram of an example of an imaging device using the photoelectric conversion device, and FIG. 7(A) is a patent application FIGS. 8(A) and 8(B) in No. 58-120755 are voltage waveform diagrams for explaining the refresh operation. 201...p type silicon substrate 203...n collector region 204...element isolation region 205...φ oxide film 206...fist capacitor electrode 207...p base region 208...n+ emitter Area 209... @ p ten area area 10... n ten area 210'... collector electrode 212... emitter electrode 213... electrode 301... output line 302, life fist scanning circuit 303... Output Amplifier Agent Patent Attorney Sekihira Yamashita Figure 1 Figure 2 Figure 3 Figure 4 Figure 7 Figure 8 (A) (B

Claims (3)

[Claims] (1) A first region made of a semiconductor of one conductivity type to form a control electrode region, and a semiconductor of an opposite conductivity type to form a main electrode region arranged to sandwich the first region above and below, respectively. 2nd and 3rd
a fourth region formed under the third region and made of a semiconductor of one conductivity type; and a semiconductor transistor configured to use the first region and the fourth region as main electrode regions. 1. A photoelectric conversion device comprising: an insulated gate electrode for controlling a region of No. 3; (2) The photoelectric conversion device according to claim 1, wherein the insulated gate electrode is capable of controlling the potential of the first region via an insulating layer. (3) The photoelectric conversion device according to claim 2, wherein the gate electrode is formed in an element isolation region for electrically isolating the semiconductor transistor from other adjacent parts. .