JPS63126327A - Reception level detecting circuit - Google Patents
Reception level detecting circuitInfo
- Publication number
- JPS63126327A JPS63126327A JP61273483A JP27348386A JPS63126327A JP S63126327 A JPS63126327 A JP S63126327A JP 61273483 A JP61273483 A JP 61273483A JP 27348386 A JP27348386 A JP 27348386A JP S63126327 A JPS63126327 A JP S63126327A
- Authority
- JP
- Japan
- Prior art keywords
- level
- signal
- circuit
- detection circuit
- electric field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 65
- 230000005684 electric field Effects 0.000 claims description 21
- 230000001629 suppression Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Monitoring And Testing Of Transmission In General (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は無線機等において、その受信信号の電界レベ
ルを検出する受信電界レベル検出回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a received electric field level detection circuit for detecting the electric field level of a received signal in a radio device or the like.
第３図（ａｌは従来のこの種の受信レベル検出回路を示
すブロック図であり、因において（１１は受信機に入力
された第１中間周波信号（以下ＩＦ１Ｆ１信号す）から
第２甲間周波信号（以下ＩＦ２信号と示す）に変換する
ミクサ回路、（２１はこのミクサ回路ｆｉｌから出力さ
れたＩＦ２信号の雑音を除去するバシドパスフィルタ回
路、（３）はフィルタ回路（２＋を通って雑音除去され
たＩＦ２信号を増幅する増幅回路、（４１は増幅回路（
３）の出力レベルに比例したＤｏレベルを出力する受信
電界レベル検出回路（Ｒ８ＳＩ） 、ｆ５＋は入力され
たＩＦＩ信号のレベルに比例したＤＣレベルを出力する
ダイオード検波回路、（６１は受信電界レベル検出回路
（５１の出力レベルとダイオード検波回路（５１の出力
レベルを加算して、受信レベルを出力する加算回路であ
る。FIG. 3 (Al is a block diagram showing a conventional reception level detection circuit of this type, and in this case, 11 is a block diagram of a second intermediate frequency signal from the first intermediate frequency signal (hereinafter referred to as IF1F1 signal) input to the receiver. A mixer circuit that converts the signal (hereinafter referred to as IF2 signal), (21 is a bassid pass filter circuit that removes noise from the IF2 signal output from this mixer circuit fil, and (3) is a filter circuit that removes noise through 2+. An amplifier circuit that amplifies the removed IF2 signal (41 is an amplifier circuit (
3) a received electric field level detection circuit (R8SI) that outputs a Do level proportional to the output level, f5+ is a diode detection circuit that outputs a DC level proportional to the level of the input IFI signal, (61 is a received electric field level detection circuit) This is an adding circuit that adds the output level of the circuit (51) and the output level of the diode detection circuit (51) and outputs the received level.
次に動作について説明する。受信機に入力されたＩＦＩ
信号はミクサ回路（１）でＩＦ２（ｆ号に変換される。Next, the operation will be explained. IFI input into receiver
The signal is converted to IF2 (f number) by the mixer circuit (1).
そのＩＦ２信号はフィルタ回路（２）を通り、雑音が抑
圧され増幅回路（：つ１に入力され、増幅回路（３）で
増幅される。そしてその信号は受信電界レベル検出回路
（４１で検波され、その入力レベルに比例したＤｏレベ
ルが直線的に出力される。その時の特性は第３図（１）
ｌの特性■となる。The IF2 signal passes through the filter circuit (2), noise is suppressed, and is input to the amplifier circuit (1), where it is amplified by the amplifier circuit (3).The signal is then detected by the received electric field level detection circuit (41). , a Do level proportional to the input level is output linearly.The characteristics at that time are shown in Figure 3 (1).
The property of l is ■.
すなわち、ＩＦｒ信号がＡ→Ｂに増えると受信レベル出
力（Ｒ８ＳＩ出力）はＶ人−＋Ｖｎと変化する。そして
ＩＦＩ信号がＢ以上となると受信電界レベル検出回路（
４１の出力が飽和し、Ｈ−＋Ｃとなっても、受信レベル
出力はＶＢのままとなる。That is, when the IFr signal increases from A to B, the reception level output (R8SI output) changes to V person - +Vn. When the IFI signal exceeds B, the received electric field level detection circuit (
Even if the output of 41 is saturated and becomes H-+C, the reception level output remains VB.
そこで、この特性を伸ばすために、ダイオード検波回路
（５１と加算回路（６１を用いる。ＩＦＩ信号はダイオ
ード検波回路（５１に入力される。そこでＩＦＪ信号の
レベルに比例して、ＤＯレベルが出力される。Therefore, in order to improve this characteristic, a diode detection circuit (51) and an adder circuit (61) are used. The IFI signal is input to the diode detection circuit (51). There, the DO level is output in proportion to the level of the IFJ signal. Ru.
このダイオード検波回路（５１は、ＩＦ１Ｆ１信号以上
の時検波し、ダイオード特性に比例したＤＯレベルが出
力される。This diode detection circuit (51) detects when the IF1F1 signal or more is detected, and outputs a DO level proportional to the diode characteristics.
この出力レベルと受信電界レベル検出回路（４）との出
力レベルが加算回路（６：で加算され、受信レベルとし
て出力される。その時の特性が第３図（１）ｌの特性■
の線となる。１２１人力Ａ −＋ ７３の時、受信レベ
ル出力（Ｒ８ＳＩ出力） ハＶＡ −ＶＢと変化、ｌ−
＋Ｑの時、ＶＢ −ｅ Ｖｃとなり、受信レベル特性の
ダイナミックレシジが広くなる。This output level and the output level of the received electric field level detection circuit (4) are added by the adder circuit (6) and output as the received level.The characteristics at that time are the characteristics shown in Figure 3 (1) l.
The line becomes 121 Human power A −+ When 73, reception level output (R8SI output) changes to VA −VB, l−
+Q, VB -e Vc, and the dynamic range of the received level characteristics becomes wider.
従来の受信レベル検出回路は以上のように構成されてい
るので、２つの検波出力を合成する場合、加算回路が必
要で部品点数が多くなり、消費電流も多くなるという問
題点があった。Since the conventional reception level detection circuit is configured as described above, when combining two detected outputs, an adder circuit is required, which increases the number of components and consumes a large amount of current.
この発明は上記のような問題点を解消するためになされ
たもので、ダイナミック・レンジの低下をきたすことな
く部品点数および消費電流を少なくすることができる受
信レベル検出回路を得ることを目的とする。This invention was made to solve the above-mentioned problems, and the object is to obtain a reception level detection circuit that can reduce the number of parts and current consumption without reducing the dynamic range. .
この発明に係る受信レベル検出回路は、受信電界レベル
検出回路の出力レベルとダイオード検波回路の出力レベ
ルを加算する加算機能を、ダイオード検波回路内にもた
せたものである。The reception level detection circuit according to the present invention has an addition function within the diode detection circuit that adds the output level of the reception electric field level detection circuit and the output level of the diode detection circuit.
この発明におけるダイオード検波回路は受信市界レベル
検出回路から入力される直流レベルに、自らの回路で横
波した検波出力レベルを加算し出力するという、検波機
能と加算機能を有する。The diode detection circuit according to the present invention has a detection function and an addition function of adding the detection output level transversely waved by its own circuit to the DC level input from the receiving market level detection circuit and outputting the result.
以下、この発明の一実施例を図について説明する。９！
ＩＪ１図（ａｌにおいて、 （１１は受信機に入力され
たＩＦＩ信号からＩＦ２信号に変換するミクサ回路、（
２）はこのミクサ回路ｔｌ＋から出力されたＩＦ２信号
の雑音を除去するフィルタ回路、（３）はフィルタ回路
（２）を通って雑音除去されたＩＦ２信号を増幅回路、
（４）は増幅回路（３）の出力レベルに比例したＤＣレ
ベルを出力する受信電界レベル検出回路、（７）はＩＦ
１Ｆ１信号イオード検波し、ｌｆｔ１［号に比例したＤ
Ｃｔレベルを出力すると共に、受信電界レベル検出回路
（４）からの出力レベルを加算し、受信レベル信号とし
て出力するダイオード素子Ｄｉ 、 Ｄ２ 、コンデン
サ素子０１により構成されているダイオード検波回路で
ある。An embodiment of the present invention will be described below with reference to the drawings. 9!
In IJ1 diagram (al), (11 is a mixer circuit that converts the IFI signal input to the receiver into an IF2 signal, (
2) is a filter circuit that removes noise from the IF2 signal output from this mixer circuit tl+, (3) is an amplification circuit for the IF2 signal from which noise has been removed after passing through the filter circuit (2),
(4) is a received electric field level detection circuit that outputs a DC level proportional to the output level of the amplifier circuit (3), and (7) is an IF
1F1 signal iode detection, D proportional to lft1[
This diode detection circuit is composed of diode elements Di and D2 and a capacitor element 01, which outputs the Ct level, adds the output level from the received electric field level detection circuit (4), and outputs the result as a received level signal.
このような構成において、受信機に入力されたＩＦＩ信
号は、ミクサ回路（１）でＩＦ２信号に変換されフィル
タ回路（２）で雑音が抑圧され、増幅回路（３）に入力
される。増幅回路（３）で増幅されたＩＦ２信号は受信
電界レベル検出回路（４１で検波され、そのＩＦ２信号
レベルに比例したＤＣレベルが出力される。In such a configuration, the IFI signal input to the receiver is converted into an IF2 signal by the mixer circuit (1), noise is suppressed by the filter circuit (2), and the signal is input to the amplifier circuit (3). The IF2 signal amplified by the amplifier circuit (3) is detected by the received electric field level detection circuit (41), and a DC level proportional to the IF2 signal level is output.
そのＤＣレベル信号はダイオード検波回路（７）のダイ
オード素子１）１ 、 ］）２を通り受信レベルとして
出力される。第１図（１）ｌにおいてＩＦＩ 信号のレ
ベルがＢ以上なら、ダイオード検波回路（７）は検波機
能が働かず、受信電界レベル検出回路（４１からの出力
レベルをそのまま出力する。ＩＦＩ信号がＢ以上になる
とダイオード検波回路（７）が検波し、ＩＦＩ信号に比
例し、ＤＣｉレベルを出力する。ＩＦｘ信号がＢ以上に
なると受信電界レベル検出回路（４１からの受信レベル
がダイオード検波回路に入力される。そして、このダイ
オード検波回路（７）での検波レベルが受信電界レベル
検出回路（４）からの受信レベルに加算され受信レベル
として出力される。ＩＦＩ信号Ｂ→０の間がこのダイオ
ード検波回路（７）によシ広げられたところである。The DC level signal passes through the diode elements 1)1, ])2 of the diode detection circuit (7) and is output as a reception level. In FIG. 1 (1) l, if the level of the IFI signal is B or higher, the diode detection circuit (7) does not have a detection function and outputs the output level from the received electric field level detection circuit (41) as it is.If the IFI signal is B When the level is above B, the diode detection circuit (7) detects the signal, which is proportional to the IFI signal, and outputs the DCi level.When the IFx signal becomes above B, the reception level from the reception electric field level detection circuit (41) is input to the diode detection circuit. Then, the detection level in this diode detection circuit (7) is added to the reception level from the reception electric field level detection circuit (4) and output as the reception level.The period between IFI signal B→0 is the detection level of this diode detection circuit. (7) It has been expanded.
また、上記実施例では、ダイオード検波回路で検波され
る信号はＩＦＬ信号であったけれども、このダイオード
検波回路を挿入する位置は、工Ｆ２信号のラインであっ
てもよく、上記実施例と同様の効果を奏する。Furthermore, in the above embodiment, the signal detected by the diode detection circuit is an IFL signal, but the position where this diode detection circuit is inserted may be on the F2 signal line, and the same signal as in the above embodiment may be used. be effective.
＊ ２ ｅ （ａ＋にその一実施例を示す。受信された
ＩＦ１Ｆ１信号クサ回路ｉｌｌでＩＦ２信号に変換され
、フィルタ回路（２１で雑音が抑圧され増幅回路（３１
で増幅され、受信電界レベル検出回路（４１に入力され
る。この回路からＩＦＩ信号に比例したＤＯレベルが出
力され、受信レベル出力となる。この時の特性は第２図
（ｂｌの特性■の線となシ、受信レベル検出のダイナミ
ツフレ〉ジはＩＦ１Ｆ１信号→Ｂのレベル範囲となる。*2 e (An example is shown in a+. The received IF1F1 signal is converted into an IF2 signal by the filter circuit (21), the noise is suppressed by the filter circuit (21), and the signal is sent to the amplifier circuit (31).
This circuit outputs a DO level proportional to the IFI signal, which becomes the received level output.The characteristics at this time are shown in Figure 2 (Characteristics of bl). The dynamic range of reception level detection is within the level range of IF1F1 signal→B.
ここでＩＦ２信号ラインにダイオード検波回路（７）を
挿入し、受信電界レベル検出回路（４１からの出力レベ
ルを入力すると、ダイオード検波回路（７）で加算され
、受信レベル検出のダイナミックレンジがＩＦ１Ｆ１信
号−４０のレベル間の範囲となり広がる。Here, a diode detection circuit (7) is inserted into the IF2 signal line, and when the output level from the received electric field level detection circuit (41) is inputted, the diode detection circuit (7) adds it, and the dynamic range of reception level detection is determined by the IF1F1 signal. The range is between -40 levels and widens.
以上のようにこの発明によればダイオード検波回路に、
加算回路の機能を持たせたので、部品点数が減少安価に
でき、また消費電流の少ないものが得られる効果がある
。As described above, according to the present invention, in the diode detection circuit,
Since it has the function of an adder circuit, the number of parts can be reduced, the cost can be reduced, and the current consumption can be reduced.
第１図（ａ）および（ｂ）はこの発明の一実施例による
受信レベル検出回路のブロック図およびその特性図、第
２図（ａ）および（ｂｌはこの発明の他の実施例を示す
受信レベル検出回路のブロック図およびその特性図、第
３［ｆｆ１（ａ）および（ｂ）は従来の受信レベル検出
回路のブロック図およびその特性図である。
（１）はミクサ回路、（２１はフィルタ回路、（３１は
増幅回路、（４）は受信電界レベル検出回路、（７１は
ダイオード検波回路。
なお、図中同一符号は同一、又は相当部分を示す。FIGS. 1(a) and (b) are block diagrams and characteristic diagrams of a reception level detection circuit according to an embodiment of the present invention, and FIGS. A block diagram of a level detection circuit and its characteristic diagram, 3rd [ff1 (a) and (b) are a block diagram of a conventional received level detection circuit and its characteristic diagram. (1) is a mixer circuit, (21 is a filter (31 is an amplifier circuit, (4) is a received electric field level detection circuit, and (71 is a diode detection circuit.) In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (2)
に応じた直流レベルに変換する受信電界レベル検出回路
と、この受信電界レベル検出回路より前段側の受信信号
を検波出力すると共にその検波出力レベルに上記受信電
界レベル検出回路の出力レベルを加算出力するダイオー
ド検波回路を備えた事を特徴とする受信レベル検出回路
。(1) A received electric field level detection circuit that converts the received signal input through the receiver into a DC level according to the signal level, and a received electric field level detection circuit that detects and outputs the received signal at the stage before the received electric field level detection circuit. A reception level detection circuit comprising a diode detection circuit that adds and outputs the output level of the reception electric field level detection circuit to the output level.
入力し、ダイオード検波回路へは第１あるいは第２中間
周波信号を入力した事を特徴とする特許請求の範囲第１
項の受信レベル検出回路。(2) Claim 1 characterized in that the second intermediate frequency signal is input to the received electric field level detection circuit, and the first or second intermediate frequency signal is input to the diode detection circuit.
Term reception level detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61273483A JPS63126327A (en) | 1986-11-17 | 1986-11-17 | Reception level detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61273483A JPS63126327A (en) | 1986-11-17 | 1986-11-17 | Reception level detecting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63126327A true JPS63126327A (en) | 1988-05-30 |
Family
ID=17528535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61273483A Pending JPS63126327A (en) | 1986-11-17 | 1986-11-17 | Reception level detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63126327A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990055485A (en) * | 1997-12-27 | 1999-07-15 | 구자홍 | Digital signal level measuring device |
-
1986
- 1986-11-17 JP JP61273483A patent/JPS63126327A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990055485A (en) * | 1997-12-27 | 1999-07-15 | 구자홍 | Digital signal level measuring device |
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