JPS63126244A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive an increase in the density of elements by a method wherein a semiconductor is adhered on a substrate, the elements are formed at the prescribed regions of the adhered semiconductor and element isolation regions are each formed between the element regions. CONSTITUTION:A Ti metal layer 13 and a Pt metal layer 14 are formed on a poly Si substrate 11 through an insulating layer 15, while an N<+> diffused layer 16, an insulating layer 15, a Ti metal layer 13 and a Pt metal layer 14 are formed in order on the lower surface of a P-type Si semiconductor 12. Then, the respective Pt metal layers 14 and 14 of this substrate 11 and the Si semiconductor 12 are superposed and the Si semiconductor is adhered on the substrate. Then, after the whole upper surface of the P-type Si semiconductor 12 is subjected to smoothing etching, transistor regions 21 and resistance regions 22 are formed at the prescribed regions of the Si semiconductor 12. Then, the semiconductor in the gaps between the element regions 21 and 22 is removed and an insulator 25 for isolating elements is filled in these parts. Thereby, the intervals between the element regions 21 and 22 are sufficiently narrowed and an increase in the density of the elements can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a plurality of elements are formed on a semiconductor such as a silicon wafer to constitute an integrated circuit.

[Conventional technology]

Since a monolithic semiconductor integrated circuit has a plurality of elements formed on a single semiconductor substrate, it is necessary to electrically isolate and insulate each element. For this reason, in the past, each element region was separated by a pn junction, and by applying a reverse bias to the substrate, each element region was floated and insulated.

An example of a conventional method for manufacturing a semiconductor integrated circuit in which each element region is separated by a pn junction will be described with reference to FIG. 9. First, an n-type impurity is selectively diffused into a predetermined location on the main surface of the p-type wafer 1 to form an n+-type buried layer 2.2, and then an n-type epitaxial layer is formed on the main surface of the p-type wafer 1. Further, only the upper region of the n+ type buried layers 2, 2 is left as n-type layers 3, 3, and n-type impurities are selectively diffused into other epitaxial layers to form p-type diffusion layers 4...・
Finally, elements are formed in each of the n-type regions 2 to 3, which are separated into islands, each consisting of each n+-type buried layer 2 and an upper n-type layer 3, thereby forming a semiconductor integrated circuit. complete. The semiconductor integrated circuit manufactured in this way is
If the p-type wafer 1 is connected to the lowest potential, the elements formed in each island-shaped n-type region 2 to 3 will be electrically insulated by the reverse bias of the pn junction.

[Problem that the invention seeks to solve]

However, such conventional methods for manufacturing semiconductor integrated circuits have had the drawback of hindering higher density of elements.

That is, in the case of the example shown in FIG. 9, for example, the n-type regions 2 and 3 are separated into islands by selectively diffusing the n-type epitaxial layer to form the p-type diffusion layer 4. Diffusion and other methods such as selective etching using photoetching technology gradually spread the diffusion region and removal region not only in the thickness direction of the layer but also behind the opening edge, so the layer to be diffused and removed is thick. This also increases the spread of the diffusion region and removed region in the upper layer to the periphery. Therefore, in order for the p-type diffusion layer 4 to actually reach the p-type wafer 1 and reliably separate each n-type layer 3, the distance between each n-type region 2 and 3 must be at least 2 times the thickness of the epitaxial layer. You must save at least double that amount. However, in the conventional method for manufacturing semiconductor integrated circuits, a pn.
Since it is necessary to form the n-type layer 3 for providing a junction, the epitaxial layer must be made thicker than necessary for forming the element. Therefore, as this epitaxial layer becomes thicker, the spacing between each n-type region 2 and 3 must also be widened, which hinders the high density of elements formed in these n-type regions 2 and 3. be.

Further, in a semiconductor integrated circuit manufactured by such a method, each of the n-type regions 2 to 3 in which each element is formed is p-type.
Since they are separated by an n-junction, there is also the drawback that the barrier capacitance of this pn-junction significantly deteriorates high frequency characteristics.

Furthermore, in the semiconductor integrated circuit manufactured by such a method, since a reverse bias is applied to the p-type wafer 1,
Another drawback was that the withstand voltage of each element became low.

[Means for solving problems]

In order to solve the above problems, the method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of bonding a semiconductor to a substrate, a step of forming an element in each predetermined region of the bonded semiconductor, and a step of forming an element between each element region. The method is characterized by a step of removing the semiconductor in the gap and, if necessary, filling the portion from which the semiconductor has been removed with an insulator.

[For production]

Since the base body is used to support each element region separated by removing the semiconductor in the gap by its rigidity, it may be made of an insulator, a semiconductor, a metal body, or other conductive body. Adhesion is performed by pressurizing metal or alloy layers formed on the bonding surfaces of the substrate and semiconductor at high temperature, or by other reliable bonding means. Furthermore, after bonding, it is preferable to process the semiconductor to be thin and smooth before incorporating the element. Furthermore, each element region to be separated in a later process must be electrically insulated, so if the adhesive layer or the substrate is conductive, an insulating layer must be formed in advance on the adhesive surface of the semiconductor. put.

Elements formed in semiconductors are active elements such as transistors and diodes, or passive elements such as resistors. These elements are formed by conventional semiconductor integrated circuit manufacturing processes such as impurity diffusion or ion implantation on a semiconductor, formation of an epitaxial layer, photoetching technology, selective etching technology, formation of an insulating film, and electrode formation. . At this time, since each element region does not need to be separated by a pn junction, the thickness of the semiconductor may be the minimum thickness necessary to form each element.

The semiconductor between each element region is removed by selective etching using photoetching technology. This removal of the semiconductor is performed until the substrate, the adhesive layer between the substrate and the semiconductor, or the insulating layer of the semiconductor is reached, thereby reliably electrically separating and insulating each element region.

This semiconductor removal process is generally performed during the element formation process, followed by the formation of an insulating film, electrode formation, etc. The surface of a semiconductor integrated circuit will eventually be covered with an insulating film for protection, but if this continues, unevenness will become severe between the area where the semiconductor is removed and the element area, especially when multilayer wiring is applied. Since there is a risk of disconnection in the wiring between elements, the recesses after the semiconductor has been removed are filled with an insulator as necessary to flatten the surface.

〔Example〕

An embodiment of the present invention will be described below based on FIGS. 1 to 6.

In this example, a wafer-shaped polysilicon substrate 11 is used as the base, and a wafer-shaped p-type silicon 12 with a (100) crystal plane is used as the half-gate body. Ti metal layer 13 and p
A case in which a t-metal layer 14 is used is shown.

First, as shown in FIG. 2, the polysilicon substrate 11 is
After forming an insulating layer 15 on the entire upper surface, a Ti metal layer 1 is formed.
3 and the PT metal layer 14 are formed in an overlapping manner. The p-type silicon 12 is formed by forming an n+ type scattering layer 16 on the entire lower surface, further forming an insulating layer 15 on the entire lower surface, and then forming a Ti metal layer 13 and a PT metal layer 14 overlappingly. Insulating layer 1
5 is Sing, SiN or /Ij2. It is made of O or a multilayer film of these, and is formed by a thermal oxidation method, a low-temperature vapor phase epitaxy method, a sputtering method, or the like. Ti metal layer 13 and P
The t-metal layer 14 is formed by continuous sputtering or continuous electron beam evaporation. The Ti metal layer 13 is well compatible with the oxide film of the insulator [15], and the Ti metal layer 13 and the PT metal layer 1
Since the metal layers 4 are also formed continuously in the vacuum chamber, these metal layers 13 and 14 are firmly adhered to the polysilicon substrate 11 and the p-type silicon 12. The n + -type scattering layer 16 is formed by diffusing n-type impurities into predetermined positions of the p-type silicon 12 .

Next, as shown in FIG. 3, the polysilicon substrate 11 and the p-type silicon 12
are placed on top of each other and bonded by applying a predetermined temperature and pressure. Normally, a metal layer to which pressure is applied starts to firmly adhere in a temperature range of 40% to 50% of the melting point of the metal. In the case of PT, this adhesion starting temperature is 88
Since the temperature is about 0°C, here it is heated to 890°C and pressure is applied. In this case, since Ti and Pt are unlikely to cause a metal reaction, the Ti metal layers 13 and the PT metal layer 14, which are bonded and integrated, maintain a stable state. The above steps correspond to the "step of bonding a semiconductor to a base" which is a component of the present invention.

When the polysilicon substrate 11 and the p-type silicone 2 are bonded together as described above, as shown in FIG. After forming the p-type silicon 17, the entire upper surface of the p-type silicon 12 is smoothed and etched.

The protective layer 17 is for protecting the polysilicon substrate 11 from the etching solution during smoothing etching, and is
Metal double film of iAu and CrCu, or SiOz formed by low temperature vapor phase epitaxy or sputtering
, StN or the like. Smooth etching is a thickly sliced plate to provide rigidity for handling convenience.
This is an operation in which the mold silicon 12 is cut down to the minimum thickness necessary for forming the element. The etching solution is K, which can preferentially etch the (100) plane of the p-type silicon 12.
Use an aqueous solution of OH or NaOH. Incidentally, etching is performed in advance to a predetermined depth of about several μm on the bottom surface of the p-type silicon 12, at a portion corresponding to the scribe line.
If it is covered with an i0g film or the like, smooth etching up to a thickness of several μm can be performed with high precision by stopping etching when the SiO□ film is exposed during smooth etching. .

Further, polishing may be performed as necessary during this smooth etching.

When the p-type silicon 12 reaches a predetermined thickness by smooth etching, the polysilicon substrate 1 is first etched as shown in FIG.
After removing the insulation layer 17 on the lower surface of the p-type silicon 12, transistors, resistors, etc. are formed at predetermined positions on the p-type silicon 12. The protective layer 17 is removed by etching using an etching solution compatible with the composition of the film. To form a transistor in p-type silicon 12, first base layers 18 are formed at predetermined positions by selectively diffusing n-type impurities, and emitter layers are further formed within these base layers 18 by selectively diffusing n-type impurities. This is done by forming 19 and 19, respectively. The resistor is formed by selectively diffusing n-type impurities simultaneously with the formation of the base layer 18 to form the resistor layer 20.

Selective diffusion is performed by first forming an insulating film such as SiO□ or SiN on the p-type silicon 12 by thermal oxidation or low-temperature vapor phase growth, and then etching the insulating film at predetermined positions using photo-etching technology, selective etching technology, etc. This is done by opening a window, diffusing impurities in this state, selectively diffusing the impurity only into the layer below the opening, and finally removing the insulating layer by etching. Note that the highest processing temperature during the formation of this transistor, etc. is about 1000°C when forming the base layer 18, but the temperature at which the TiPt alloy system may melt is about 1300°C. glued p
The metal layer 14 does not peel off and is stable. The above steps correspond to a part of the "step of forming elements in respective predetermined regions of the bonded semiconductor" which is a component of the present invention.

After each element is formed in the p-type silicon 12 in this way, as shown in FIG.
- Form 21 and resistance region 22. p-type silicon 12
The removal is carried out using a photo-etching technique or a selective etching technique using a hydrofluoric acid-based or nitric acid-based etching solution.

In addition, considering the case where a pinhole is generated in the insulating layer 15 below the p-type silicon 12, this p-type silicon 1
2, if the insulating layer 15, the upper Ti metal layer 13, the integrated Pt metal layer 14, and the lower Ti metal layer 13 are also removed, the isolation of each element region 21 and 22 can be completely isolated. can be taken as a thing. The above steps correspond to the first step of the component of the present invention, ``the step of removing the semiconductor in the gap between each element region and, if necessary, filling the portion from which the semiconductor has been removed with an insulator.''

Finally, as shown in FIG.
An insulating film 23 is formed on the entire upper surface of the exposed part of the insulating layer 15 formed on the p-type silicon 12 and the p-type silicon 12.
A semiconductor integrated circuit is completed by opening contact holes at necessary locations and forming an electrode film 24 in a predetermined pattern. The insulating film 23 is made of 5in2 or SiN, etc.
It is formed by low temperature vapor phase epitaxy or sputtering. The contact hole is opened by removing a portion of the insulating film 23 by selective etching using photoetching technology. The electrode film 24 is made of A2, MOLW, MoS
It is made of a conductor such as iz, WSi2, etc., and can be deposited using electron beam evaporation, sputtering, or low-pressure plasma C
After forming the conductor film on the insulating film 23 and the contact hole by a vapor deposition method or the like, the conductor film is etched into a predetermined pattern by selective etching using photoetching technology. Ru. The above steps correspond to the remaining portions of the "step of forming elements in respective predetermined regions of the bonded semiconductor" which is a component of the present invention.

In the case of the semiconductor integrated circuit shown in FIG. 1, each of the element regions 21 and 22 has a convex shape, so there is a risk that the electrode film 24 may be disconnected at the edge portion. Further, when the electrode film 24 is formed into a multilayer wiring, there is a greater risk of disconnection. For this reason, as shown in FIG. 7, after forming the insulating film 23, a planarizing material 25 is filled between each element region 2 and 22.
The electrode film 24 may be formed after the surface is flattened. The flattening material 25 is made of polyimide or 5 which is an insulator.
Using iOz, the space between each element region 21 and 22 is filled by an etch-back method or a sputtering method.

The above steps correspond to the latter stages of the "step of removing the semiconductor in the gaps between the respective element regions and, if necessary, filling the portions from which the semiconductor has been removed with an insulator" which is a component of the present invention.

In this embodiment configured as described above, p-type silicon 12
Since the p-type silicon 12 can be thinned down to the minimum thickness for device formation, the distance between each device region 21 and 22 from which this p-type silicon 12 is removed can be made sufficiently narrow, and each device region on the semiconductor integrated circuit can be It becomes possible to arrange elements at high density.

Note that in this embodiment, a polysilicon substrate 11 is used as the base.
However, insulators such as sapphire and ceramics, semiconductors such as single crystal silicon wafers, or MO% W% Fe,
Single-element metal plate such as Ti or WSi, MoSi,
An alloy metal plate such as TiSi or the like may also be used. In addition, in this example, as a semiconductor, the crystal plane is (100)
Although p-type silicon 12 of
Other than i, other semiconductors such as m-v group semiconductors such as GaAs and InP may be used. Furthermore, in this example,
A multilayer film of a Ti metal layer 13 and a Pt metal layer 14 was used to bond the polysilicon substrate 11 and p-type silicon 12, but a multilayer film of Cr and Cu, Cr and Pt, or Ti and Ni, TiSi, etc. ,MoS i,,WS 1SCrCo
or a single alloy such as CrPt or Cr and TiSi,
A multilayer film of a single metal such as Ti and MoSi or Ti and WSi and an alloy can also be used.In addition to the same type of film, a multilayer film of Ti and pt may be formed on one side and T on the other side.
It is also possible to form a multilayer film of i and Pd and press these dissimilar metals together (other methods are also possible if reliable adhesion can be obtained.Also, in this example, when adhering Although the case where the layer is formed on the entire adhesive surface is shown, taking into account the difference in thermal expansion coefficient, etc., as shown in Fig. 8,
It may be formed only on a part of the polysilicon substrate 11 or a part of the p-type silicon 12 (not shown). Also,
In this embodiment, the case of a bipolar IC has been described, but it is also possible to implement the present invention in a unipolar IC 1 such as a C-MOS or other devices.

〔Effect of the invention〕

As described above, the method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of bonding a semiconductor to a substrate, a step of forming an element in each predetermined region of the bonded semiconductor, and a step of forming a semiconductor in the gap between each element region. The structure includes the steps of removing the semiconductor and, if necessary, filling the removed portion with an insulator.

As a result, each element region is isolated and insulated by the void after the semiconductor has been removed or by the insulator filled in the void. The thickness of this semiconductor to be removed can be reduced to the minimum required for forming each element, so even if the interval between each element region is made more than twice the thickness of this semiconductor,
Each element region can be arranged sufficiently close to each other, and higher density of elements can be achieved. Further, each element region is separated by a gap or an insulator, and no barrier capacitance of a pn junction occurs as in the conventional case, so that high frequency characteristics are not degraded. Furthermore, since there is no need to apply a reverse bias as in the conventional case, there are effects such as no reduction in the withstand voltage of the element.

[Brief explanation of the drawing]

1 to 6 show one embodiment of the present invention, in which FIG. 1 is a vertical cross-sectional partial front view of a semiconductor integrated circuit, and FIG.
6 to 6 are longitudinal cross-sectional partial front views showing the manufacturing process of a semiconductor integrated circuit, and FIGS. 7 and 8 show other embodiments of the present invention, and FIG. 7 corresponds to FIG. 1. FIG. 8 is a vertical cross-sectional partial front view of yet another embodiment corresponding to the polysilicon substrate of FIG. 2, and FIG. 9 is a conventional semiconductor integrated circuit manufacturing process. It is a vertical section partial front view showing. 1 is a polysilicon substrate (substrate), 12 is p-type silicon (semiconductor), 13 is a Ti metal layer, 14 is a Pt metal layer, 2
1 is a transistor region, 22 is a resistance region, and 25 is a flattening material (insulator).

Claims (1)

[Claims] 1. The process of bonding the semiconductor to the substrate, the process of forming elements in each predetermined area of the bonded semiconductor, removing the semiconductor in the gaps between each element area, and insulating the parts where the semiconductor was removed as necessary. 1. A method for manufacturing a semiconductor integrated circuit, comprising the step of filling a semiconductor integrated circuit.