JPS63125918A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To accurately vary display density to a desired extent by providing a common driving part which generation the common electrode driving signal of a liquid crystal display element and a common driving part which inputs a pulse and is varied in the length of the driving period of a segment electrode driving signal to the liquid crystal display element corresponding to the delay period of the input pulse. CONSTITUTION:A digital signal corresponding to the display density of the liquid crystal display element is generated by an input part and supplied to a pulse generation part 27 to generate plural pulses having mutual delay periods corresponding to the digital signal. Those pulses are supplied to segment driving parts 17 and 20 to vary the length of the driving period of the segment electrode driving signal to the liquid crystal display element corresponding to the delay periods. The segment electrode driving signal which is varied as mentioned above is supplied to the liquid crystal display element together with a common electrode driving signal from the common driving part 15 to control its density. Thus, the density of the liquid crystal display element can be controlled with the digital signal, so the display density can accurately be variable to a desired extent.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal FFI operating circuit suitably used for adjusting the concentration of liquid crystal.

Prior Art FIG. 5 is a circuit diagram of a power supply circuit 1 for explaining the prior art. Conventionally, density adjustment of a display section using a liquid crystal has been achieved by using a variable resistor VR realized by a variable resistor or a resistor larg in a power supply circuit. That is, by changing the resistance value of the variable resistor VR, the power supply voltage Vcc is changed, and the drive voltage VD applied to the liquid crystal of the display section can be arbitrarily changed, thereby adjusting the liquid crystal concentration of the display section. was.

FIG. 6 is a waveform diagram of the applied voltage applied to the liquid crystal using the power supply circuit 1. As mentioned above, the drive voltage VD applied to the liquid crystal is determined by the resistance value of the variable resistor VR. For example, if the resistance value of the variable resistor VR is decreased, line J?
As shown in 2, the driving voltage VD becomes thick (becomes thicker), and therefore the display density becomes darker.

On the other hand, if the resistance value is increased, the driving voltage VD becomes smaller as shown in line No. 3, and the display density becomes thinner.

Generally, the duty (common side @) of the liquid crystal drive is D,
If the bias resistor R1/(R1+R2+R3) is the B1 drive voltage VD, the liquid crystal lighting voltage Von.

The smoke extinguishing voltage Voff is expressed by the following equation.

Von=A completed -1)/D-(VD/B)...(1
) Voff= (B-2)2+<D-1)/D ・(
V D/B)...(2) As is clear from the above equations (1) and (2), the lighting voltage V.

n, Voff can be expressed as a function of the drive voltage VD.

Problems to be Solved by the Invention In this method of adjusting the liquid crystal density by changing the resistance value of the variable resistor VR, it is difficult to set the display section to a specific density.

That is, since the resistance value is changed manually and in an analog manner, it is difficult, for example, to reproduce the concentration once set.

Further, in order to change the resistance value, a variable resistor or a resistor hook must be provided, which hinders miniaturization of the liquid crystal drive circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal drive circuit that solves the above-mentioned problems, has a simple configuration, and can accurately change display density to a desired degree.

Means for Solving the Problems The present invention provides: an input section from which a digital signal corresponding to the display density of a liquid crystal display element is generated; and a plurality of pulses having mutual delay periods corresponding to the digital signals from the input section. a common drive unit that generates a common electrode drive signal for the liquid crystal display element; and a common drive unit that generates a common electrode drive signal for the liquid crystal display element; Including a common drive part whose length can be changed! This is a characteristic liquid crystal drive circuit.

In the liquid crystal drive circuit according to the present invention, a digital signal corresponding to the display density of the liquid crystal display element generated from the input section is given to the pulse generating section, and the pulse generating section has a delay period between them corresponding to this digital signal. Multiple pulses are generated. This pulse is applied to the segment drive section, and the length of the drive period in the segment electrode drive signal to the liquid crystal display element is changed in accordance with the delay period. The segment electrode drive signal changed in this way is given to the liquid crystal display element together with the common electrode drive signal from the common drive section to control the density thereof.

Embodiment FIG. 1 is a circuit diagram of a liquid crystal drive circuit 10 which is an embodiment of the present invention. The liquid crystal driving circuit 10 includes a power supply circuit 11, a frequency dividing circuit 12 that divides the frequency of a reference clock 111, a segment driving section 13 that drives segment side electrodes, and a delay circuit 14.
, a common drive section 15 that drives the common side electrode, a concentration control signal generation section 16, and the like. In this embodiment, the liquid crystal drive circuit 10 will be explained based on the 1/4 duty, that is, the number of commons is four. Therefore, the segment drive circuit 13 has four segment drive circuits 17, 18, 1
9.20, and the common drive section 15 also consists of four common drive circuits 21.22, 23.24.

The concentration control signal generating section 16 includes a frequency dividing circuit 25 and an input circuit 26.
and a concentration control pulse generator 27 (61).

The power supply circuit 11 includes four resistors R1, R2, R3°R4,
It is composed of a pH field effect transistor (hereinafter abbreviated as a P-type transistor) Tri and an N-type field effect transistor (hereinafter abbreviated as an N-type transistor) Tr2. Four resistors R1, R2, R3, R4 are connected in series in this order, and one end of resistor R1 is connected to the line J! 5 to the source of the P-type transistor Tri;
This drain is connected to the connection point 28A between resistor R1 and resistor R2. On the other hand, the drain of the N-type transistor Tr2 is connected to the connection point 28B between the resistors R3 and R4, and the source is grounded. Further, one end of the resistor R4 is also grounded.

Above this, the TIL source circuit 111 is 1 soil, line 1
The power supply voltage +Vcc is supplied to line 5, and the drive voltage VD from line 5 is the connection between resistor R2 and resistor R3, 4.28
It is applied to the common drive unit 15 together with the output voltage VM from M. On the other hand, both the output voltage VA of the connection point 28A and the output voltage VB of the connection point 28B are given to the segment drive section 13.

The frequency dividing circuit 12 includes a T-type 7-lip 70-tube (hereinafter abbreviated as T-FF) 29 that divides the reference clock h1 by 2, and a T-FF 30 that divides the output h2 of the T-FF 29 by 2.
It consists of The output h3 of the T-FF 30 is applied to the segment drive unit 13, and is also applied via the inverter 31 to the dates of both the P-type and N-type transistors Tri and Tr2. Further, the output of this inverter 31 is also given to the common drive section 15.

FIG. 2 is a timing chart of the frequency dividing circuit 12, the power supply circuit 11, the segment driving section 13, the delay circuit 14, and each output waveform. (1) in the same figure is the reference clock h1
FIG. This reference clock h1 is applied to the delay circuit 14 and also to the T-FF 29, where the frequency is divided by two. (2) in the same figure is the output h2 of T-FF29.
FIG. The output h 2 of the T-FF 29 is given to the delay circuit 14 -4, the output h 2 is given to the T-FF 30,
Here, this T-
FF30 output! 13 is inverted by the inverter 31 (see (4) in the same figure), and the P type and l of the power supply circuit 11 are inverted.
/Given to each date of N-type transistors Tri and Tr2.

The figure (5) shows each connection point 28A, 28M of the power supply circuit 11,
28B is an output waveform diagram at 28B. Here, power supply circuit 11
The operation will be explained. P type trannostar Tri
When the "L" signal is input to the date, the source and drain become conductive, and when "H" is input, the N-type transistor tr2 operates in the opposite way to the P-type transistor Tri. Therefore, when an L'' signal is input to each date of the P-type and N-type transistors Tri and Tr2, the P-type transistor Tr
i becomes conductive, and the N-type transistor Tr2
is in a cut-off state. In this state, the electric voltage is
cc is directly applied to the connection point 28A as the drive voltage VD, and at the connection point 28M, the output voltage VA (
= VD), voltage drop 6 by resistance R2, connection point 28
At B, the voltage is further dropped by the resistance R3.

On the other hand, when an "H" signal is input to each date of the P-type and N-type transistors Tri and Tr2, the P-type transistor becomes cut off and the N-type transistor Tr2 becomes conductive. In this state, the connection point 28B is grounded and its potential is zero.

Also, what about connection point 28A? I! The source voltage Vcc is applied after being dropped by the resistor R1. Connect like this,
Each output voltage VA of K28A, 28M, and 28B.

The waveforms of VM and VB for the output h3 of the inverter 31 are as shown in (5) of the same figure. The high potential and low potential output levels of these output voltages VA, VM, and VB are hereinafter referred to as output levels HA, LA; HM, respectively.
, LM:HB, LB.

The configuration and operation of the delay circuit 14 will now be explained.

The delay circuit 14 includes two inverters 32゜33 and J:u4.
It is composed of two NOR circuits 34, 35 and 36, 37. This delay circuit 14 has a reference clock 1 as described above.
11 and the output h2 of the T-FF 29 are given, but these two outputs hl and h2 are supplied to the NOR circuits 34 and 36.
; 34, 35 directly, while the inverter 32
．． 33, and the output h of this inverter 32.33
l and h2 are NOR circuits 35, 37; 36, 37, respectively.
given to.

Figure 2 (6) shows four NOR circuits 34, 35, 36°3.
7 is a waveform diagram of each output hl'', h2', h3', and b4' of the circuit 7.Here, the description will focus on the NOR circuit 34.

The NOR circuit 34 has a reference clock h1 and T-F.
When the output 1]2 of F29 is input and the time is LO,
Since both inputs are “L”, the output h of the NOR circuit 34
1' becomes "H", and at time t1, the reference clock h1 is "H" and the output h2 of the T-FF 29 is "L", so the output 111' of the NOR circuit 34 becomes "L". The output h1' of the NOR circuit 34 obtains a waveform containing "H" for half a cycle of the reference clock 111 once every two cycles of the reference clock I+1, as shown in (6) in FIG. Hereinafter, in the same manner, NOR circuits 35, 36, .
The outputs h2', h3', and b4' of 37 are shown in the same figure (6).
The output h1' of the NOR circuit 34 is shown as ■, ■, ■ in the figure.
A waveform delayed by half a cycle of the reference clock h1 is obtained, and these are sent to the common drive circuits 21.22 and 23.24 of the common drive unit 15 as control signals hl' and h2, respectively.
', h3', h4'.

Next, the configuration and operation of the common drive circuit 21 will be explained. Note that the common drive circuits 22, 23, and 24 have the same configuration as the common drive circuit 21. The common drive circuit 21 includes an inverter 39, a NAND circuit 40, a NOR circuit 41, P-type trannostars Tr3 and Tr5, and N-type trannostars Tr4 and Tr6.

The control signal h1' is applied to one terminal of the NAND circuit 40, while being applied to one terminal of the NAND circuit 40 via the inverter 39.
and one terminal of the NOR circuit 41. 1±connection point 28 of the power supply circuit 11 to the sources and drains of the P-type and I/N-type trannostars Tr5 and Tr6.
The output voltage VM from M is commonly applied, and similarly applied to the other common drive circuits 22, 23, and 24. The output h3 from the inverter 31 is commonly applied to the other terminals of the NAND circuit 40 and the NOR circuit 41, and similarly applied to the other common drive circuits 22, 23, and 24.

On the other hand, the drive voltage VD from the power supply circuit 11 is applied to the source of the P type) lannostar Tr3, and is also commonly applied to the other common drive circuits 22, 23, 24, respectively. Further, the drain of the P-type transistor Tr3 is connected to the drain of the N-type transistor Tr4, and the source of the N-type transistor Tr3 is grounded. These P
The output P1 of the NAND circuit 41 and the output P2 of the NOR circuit 41 are applied to the dates of the N-type and N-type transistors Tr3 and Tr4, respectively. The drains and sources of the P-type and N-type transistors Tr3 and Tr4 are respectively commonly connected to the drain of the p-type transistor Tr5, and the output H1 from this connection point is applied to the common electrode as a common drive voltage. Similarly, the common drive voltages H2 and H are also applied from the common drive circuits 22, 23, and 24.
3, H4 is output.

FIG. 2 (7) shows each common drive circuit 2 of the common drive section 15.
1, 22, 23.24 are respective waveform diagrams of common drive voltages H1, H2, H3, and H4 outputted from.

The operation of the common drive circuit 21 with respect to the control signal hl' will be described below with reference to (4), (5), (6) (6) and (7) (7) in the same figure.

At time L[, this control signal hl'' is "H",
Since the output h3 of the inverter 31 is ``H'', N
Outputs P1 and P2 of AND circuit 40 and NOR circuit 41
Both become “L” (Output Q1 of NAND circuit 40
becomes “L” only when both inputs are “H”, and NO
The output P2 of the R circuit 41 becomes "H" only when both inputs are "L"). Therefore, the P-type transistor Tr3 becomes conductive, and the N-type transistor Tr3 becomes conductive.
-4- is in a cut-off state.

On the other hand, the date input of P-type transistor Tr5 is H
", so this is in a cutoff state. Also, since the date input of the N-type transistor Tr6 is the output h1 of the inverter 39, it is in a cutoff state. Note that the P-type and N-type transistors TrS , Tr6 perform the same operation with respect to the control signal hl'. That is, when the control signal hl" is "H", both are in a cut-off state, and when the control signal hl' is "ILL", both are in a conductive state.

Therefore, at time 10, the P-type trannostar T
Since only r3 becomes conductive, the driving voltage VD is applied to the connection point.

Next, at time t1, the control B signal h1' is "L".
'', and the output h3 of the inverter 31 remains at "H", so the output P1 of the NAND circuit 4o becomes "H",
The output P2 of the NOR circuit 41 becomes "L"', and therefore both the P-type and N-type trunk transistors Tr3 and Tr4 are cut off. On the other hand, P-type and N-type transistors Tr5. In Tr6, the control signal h1' is "L"
Therefore, both are in a conductive state.

Therefore, at time L1, only P-type and N-type transistors Tr5 and Tr6 are in a conductive state, so that
An output voltage VM is applied to the connection point.

Note that at this time L1, the output voltage VM is at the output level LM, so this is applied to the connection point. This state continues until time t2.

At time t2, the control signal 111' becomes "H" again, and the output h3 of the inverter 31 becomes "L", so the output P1 of the NAND circuit 40 becomes "H", and
Since the output h1 of the inverter 39 is "L", the NOR
The output P2 of the circuit 41 becomes "H". Therefore, the P-type transistor Tr3 continues to be cut off, and the N-type transistor Tr4 becomes conductive. On the other hand, since the control signal 111' is H'', the P-type and N-type trannostars Tr5 and Tr6 are both cut off, so at time t2, the N-type transistor T
Only r4 becomes conductive, the connection point # is grounded, and the applied voltage becomes zero.

At time t3, the control signal hl' and the output h3 of the inverter 31 are both "L", and the outputs hl' of the three inverters are "H", so the output P1 of the NAND circuit 40 is "H", and the output of the NOR circuit is 41 output P2
becomes "L". Therefore, both P-type and N-type transistors Tr3 and Tr4 are cut off. On the other hand, since the control signal hl' is L'', the P-type and N-type trannostars Tr5 and Tr6 are both in a conductive state.

Therefore, at time L3, the state is the same as at time L1, but since the output voltage VM is at the output level I]M, at time t4, where it continues to be applied until 4, the output voltage VM is at the output level I]M. Since this is exactly the same state as LO, the common drive voltage H1 is outputted from the connection point with a waveform as shown in FIG. 2 (7) (2), with this period as one cycle. Hereinafter, in the same manner, the NOR circuit 35 of the delay circuit 14
．． Common drive voltages H2, H3 from common drive circuits 22, 23.24 corresponding to respective outputs h2', h3', h4'' of 36.37.

H4 is output behind the common drive voltage H1 by half a cycle of the reference clock b1 (see (7) (7) in the same figure).

Next, the configuration and operation of the segment drive section 13 will be explained. The segment drive section includes four segment drive circuits 17.18, 19.20, and the segment drive circuit 17 is connected to other segment drive circuits 18, 19.2.
It has the same configuration as P type and N type Y Lannostar T.
r7. Tr8 and exclusive logic circuit (hereinafter referred to as EX-OR
(abbreviated as ) 42. In addition, AND circuit 6
1 is included in the segment drive circuit 17, and similarly, AND circuits 62, 63, and 64 are included in the drive circuits 18, 19, and 20, respectively. P-type and N-type transistors Try.

The source and drain of Tr8 are supplied with output voltages VA and VB from the power supply circuit 11, respectively, and are similarly supplied to the other segment drive circuits 1B and 19.20. Each drain is connected via a connection point E,
On the other hand, each date is given the output F of EX-OR42. One terminal of EX-OR42 has T- of frequency divider circuit 12.
The output 113 of the FF 30 is applied, and likewise to the segment drive circuit 18°19.20.

On the other hand, an AND circuit 61 is connected to the other terminal of EX-OR42.
1 is given to the output from the segment)1. :, tt A control signal D1 for controlling whether or not to light up the liquid crystal display is input together with a control signal T1 from a density control signal generator ff516, which will be described later. Similarly, segment drive circuits 18, 19.2
0 as well as the output from the AND circuit 62.63.64 K 2
, K 3 and K 4 are input, and these AND circuit 6
2.63.64 has control signals D 2 , D 3 , D
4 is input together with the control signal T1, and corresponding to these control signals, the dynamic voltage S 2 ,
Output S 3 and S 4.

The control signal D1 is synchronized with the reference clock h1,
For example, a waveform as shown in FIG. 2 (8) is output.

The operation of the segment drive circuit 17 will be described assuming that such a control signal D1 is applied to the AND circuit 61.

Here, the period in which the control signal T1 from the density control signal generator 16 inputted to the AND circuit 61 is "H" in 1/2 cycle of the reference clock 7 is 14/I.
However, when illustrating a waveform of 1 at the output of the AND circuit 61, for convenience, the control signal T1 is always "H".
It is assumed that This has the same waveform as the control signal D1.

When the output F of EX-OR42 is "H", the P-type trannostar Tr7 is in the cut-off state, and the N-type trannostar Tr7 is in the cut-off state.
r8 becomes conductive. Therefore, the output voltage VB is applied to the connection point E.

On the other hand, when the output F of EX-OR42 is 'L', the P-type transistor Tr7 becomes conductive, and the N-type transistor Tr5'
) Star Tr8 enters the cut-off state. Therefore, the output voltage VA is applied to the connection point E.

In this way, for example, at time 10, T-
The output h3 of FF30 is 'L'', and the AND circuit 61
Since the output of 1 is H'', the output F of EX-OR42 is H''. Therefore, output voltage VB is applied to connection point E, but since output voltage VB is at output level LB (=GND) at time 10, segment drive voltage S1 is zero.

At time t1, the output h3 of T-FF30 is “L”
'', and 1 becomes "L" at the output of the AND circuit 61, so the output F of EX-OR42 becomes "L" and the connection point E
The output level LA of the output voltage ■A is applied to the segment drive voltage S1, which is output as the segment drive voltage S1.

At time L2, the output h3 of T-FF30 is “H”.
", and the output of the AND circuit 61 also becomes H". Therefore, the output F of EX-OR42 remains at L''', and the output voltage VA is applied to the connection point E, but at time t2
, the output voltage is output level HA (=
V D ), this is the segment drive voltage S1
is output as

At time t3, the output b3 of T-FF30 is “
remains at "H", and 1 at the output of the AND circuit 61 becomes "L"
'. Therefore, the output F of EX-OR42 is H''
Therefore, the connection 7αE has the output level HB of the output voltage VB.
is applied, this is output as the segment drive voltage S1, and this state is connected until time t4.
Since the state is the same as that at time to, the segment drive voltage S1 having this period as one cycle is output from the connection point E.

This segment drive voltage S1 has a waveform as shown in FIG. 2 (9). Therefore, if this segment drive voltage S1 and the common drive voltage H1 from the common drive circuit 21 described above are applied to the liquid crystal, equivalent alternating current is obtained as shown by the solid line in FIG.

Hereinafter, in the same manner, the segment drive circuits 18, 19゜20
Segment drive voltages S 2 , S 3 , and S 4 corresponding to the control signals D 2 , D 3 , and D 4 are also output from the .

However, as mentioned above, since the control signals D1 to D4 are signals that control whether or not to turn on a predetermined liquid crystal display element, they are generally connected to the segment drive voltages 81 to S4 corresponding to these control signals D1 to D4. Drive voltage H1
.about.H4 to the liquid crystal display element, the waveform is not necessarily as shown in FIG. 3.

Next, the configuration and operation of the density control signal generating section 16 will be explained. As described above, the concentration control signal generation section 16 is composed of the frequency dividing circuit 25, the input circuit 26, and the concentration control pulse generation section 27, and the division circuit 25 includes three T-FFs 43, 44. It consists of 45 pieces. T-
The FF 43 is supplied with a reference clock hO having a frequency 16 times that of the reference clock h1 input to the T-FF 29 of the frequency dividing circuit 12.

FIG. 4 is a timing chart for explaining the operation of the concentration control signal generating section 16. (1) in the same figure is a waveform diagram of the reference clock I+O, (2) in the same figure, (3L (4)
are each output h01, hO of T-FF43, 44.45
2. It is a waveform diagram of hO3. Note that (5) in the same figure is a waveform diagram of the reference clock h1 synchronized with these. T
-FF43, 44.45 are (2) and (3)t (
4) As shown in the figure, each input signal is divided into two and outputted, and these outputs ho are used together with the reference clock bO.
1, ho 2 and bO3 are respectively connected to the four EX-ORs 50°51.52' and 5 of the concentration control pulse generating section 27.
3, and is commonly applied to the 4-person NOR circuit 54.

The input circuit 26 includes four D-FFs (D-type 7-pin 70-tube) 46.47. ．． 48.49, each with 4
Bit binary data Go, G1 . G2. G3 is input, and the clock signal CK is also input in common, and these outputs Q O, Q 1 , G2, and G3 are given to EX-ORs 50, 51, 52, and 53, respectively. 4
Bit binary data Go, Gl.

G2. There are 16 combinations of G3, and as will be described later, the density of the liquid crystal is controlled by this data. Further, the clock signal CK has the same waveform as the reference clock ho, and the clock signal CK is applied to the D-FF46, 4
By inputting to 7, 48, and 49, the output Q O, Q
1 , Q 2 , and Q 3 will be synchronized to the reference clock 110.

In the concentration control pulse generation section 27, EX-OR50
, 51, 52, and 53 are applied in parallel to a NOR circuit 55, and the output Z2 of this NOR circuit 55 is the output of the NOR circuit 55.
It is applied to the NOR circuit 56 together with the output Z1 of the R circuit 54. The output of the NOR circuit 56 is connected to the inverter 57 and T
- Each AND circuit 61162.
Commonly given to 63°64.

The output To of the inverter 57 is, for example, 1!2 cycle period T of the reference clock 111 as shown in FIG. 4(6).
Two pulses are always formed, a reference pulse α and a control pulse β, which have a rising period of 1!2 cycle period (hereinafter referred to as clock period) W of the reference clock ho during h. Note that the rising time of the reference pulse α always coincides with the start time of the period Th (time 10 in the fjS4 diagram), and the rising time of the control pulse β, that is, the rising time 10 of the reference pulse α and this control pulse β
The period Tβ (hereinafter referred to as the operation period) between the rising time of the signal and the rising time of the signal is determined by the 4-bit binary data GO-G3 input to the input circuit 26 described above. Note that this operating period Tβ is for controlling the concentration of liquid crystal, as will be described later. The reference pulse α and the control pulse β will be explained below.

First, let us consider the case where the output TO of the inverter 57 becomes "H". If this output TO is "H", then N
The output of the OR circuit 56 is "H", so at least one of the outputs z i and z2 of the NOR circuits 54 and 55 needs to be "H".

If the output of the NOR circuit 54 is "H", the four outputs, that is, the reference clock ho and the three T-F
Each output ho 1 and hO2 of F43, 44.45.

All ho3 must be "L". On the other hand, N
If the output Z2 of the OR circuit 55 is "H", EX-OR
All outputs of 50, 51, 52, and 53 must be "H", so each output Q of D-FF46~4
O-Q3 and reference clock hO, T-FF43~45
The outputs hot to h03 must match.

In other words, when the reference clock bO, the four outputs h01 to h03 of the T-FFs 43 to 45 are all L'', and the four outputs and the outputs Q of the D-FFs 46 to 49
Only in the two cases when O-Q3 match, the output TO of the inverter 57 becomes "■4".

In this way, a rising pulse is formed at the output To of the inverter 57. That is, in the former case, a reference pulse α is formed, and in the latter case, a control pulse β is formed.

Next, the generation process of the reference pulse α and the control pulse β will be explained. The frequency dividing circuit 25 is shown in FIG. 4 (1) to (4).
As is clear from the diagram, it can be regarded as a 4-bit binary counter, and the output from this is 1+03, ho
2, ho 1, ho lio.
It is possible to count from 0 to 15.

During the period corresponding to "0" in such a cyclic counting operation, that is, during one clock period WO from time 10, all outputs hO to h03 of branch station n-25 are "L".
Therefore, the output To of the inverter 57 becomes "H".

This is the reference pulse α mentioned above.

Next, the control pulse β will be explained. First, D-FF4
9,48.47.46 output Q3. Q2゜Q1
, Q O are respectively "H", "L", "H", and "H", that is, "11" in decimal notation is assumed. These outputs are EX-OR53, 52, 51, 50! : When given, the output TO of the inverter 57 becomes “H”.
'' is the output 1103 of the frequency dividing circuit 25, h
Only when O2, ho 1 and bO are "11" in decimal notation. That is, the output To of the inverter 57 becomes "H" only during the 11th @ clock period W11 from time 10. This is the control pulse β.

As is clear from the above, the number from time 10 of the clock period in which the control pulse β is generated is
The control signal G3.6, which is binary data, is input to G3.6. G2.
It matches the number corresponding to the decimal system of Gl and Go.

In this way, the reference pulse α and the rising control pulse β are:
The output TO of the inverter 57 having the inverter 57 is obtained, and this output T
O obtains, via the T-FF 58, an output T1 having an opening rising pulse of the above-mentioned operating period Tβ. Note that since this operating period Tβ is determined by the rising time of the control pulse β, WO, W 1 , W
Generation of control pulse β of No. 15 is prohibited. This is because the clock periods ImWO, W1. This is because if the control pulse β is generated at W15, it becomes impossible to distinguish between the reference pulse α and the control pulse β, and therefore the output T1 of the T-FF 58 becomes meaningless. Therefore, as a matter of course, the control signals G3 and G input to the input circuit 26
2, G 1, G O are rOJ corresponding to decimal system
, rl "汀15" is prohibited.

The control signal T1 output from the concentration control signal generating section 16 having the above configuration is composed of the four A
The control signal D1 is applied to the ND circuits 61, 62, 63, and 64.
, D 2 , D 3 , and D 4 . For example, in the segment drive circuit 17, the AND circuit 61 is supplied with the control signal D1 from the control signal T1. As a result, the control signal D1
The rising pulse of control signal T1 has an operating period of 12 minutes.
, and the remaining part is removed to obtain an output of 1 (see Figure 4 (8)).

Here, the role played by the rising pulse of the control signal D1 is the output from the segment drive circuit 17, that is, the generation time and period of the maximum level (=drive voltage VD) and minimum level (=GND) of the segment drive voltage S1. This is what determines the Further, the driving voltage VD(
The maximum level) literally determines the density of the liquid crystal. Therefore, it can be concluded that the fact that the rising pulse of the control signal D1 is changed at 1 in the output of the AND circuit 61 means that the concentration of the liquid crystal is changed accordingly.

That is, by setting the operating period T I+ to an arbitrary length, an AC waveform as shown by the broken line in FIG. 3, for example, can be obtained, and the liquid crystal concentration is determined by this.

Therefore, the duty of liquid crystal drive (number of common side) is D,
If the bias resistance R1/(R1+R2+R3) is B and the drive voltage is VD, the liquid crystal lighting voltage (On) and the clearing voltage (Voff) are expressed by the following equations.

Von= fB2・t2+(D−tN/D・(V
D/B)...(3) \'off= I(B-2)2+(D1)l
/ D ・(VD/B) ...(4)
However, L=O~1.

In this way, the concentration of the liquid crystal is determined by the segment drive voltage S
The same thing can be said about the segment drive circuits 18, 19, and 20, which is realized by changing the rising pulse width of the drive voltage VD of 1.

Therefore, in the liquid crystal drive circuit 10 according to this embodiment, the concentration of liquid crystal can be adjusted by changing the pulse width of the drive voltage without using a variable resistor or the like.

Further, since the density '/I4 adjustment is determined by 4-bit binary data, it is easy to reproduce the density once set. Furthermore, according to this embodiment, there is no need to provide a variable resistor or a resistor, which contributes to downsizing of the liquid crystal drive circuit.

Effects As described above, in the liquid crystal drive circuit according to the present invention, the density of the liquid crystal display element can be controlled by the digital signal. Therefore, it is possible to accurately change the display density to a desired degree. In addition, the display density can be controlled by
Since this is achieved by changing the length of the drive period in the segment electrode drive signal, this can be achieved without using a variable resistor or the like as described in the prior art section. Therefore, the configuration of the concentration driving circuit can be simplified.

[Brief explanation of the drawing]

@i Figure is a circuit diagram of a liquid crystal drive circuit 10 which is an embodiment of the present invention, and Figure 2 is a circuit diagram of a frequency dividing circuit 12, a power supply circuit 11, a segment drive section 13, a delay circuit 14, and a common drive circuit 15.
FIG. 4 is a timing chart showing an example of the voltage applied to the liquid crystal obtained by the liquid crystal drive circuit 10. FIG. , 5th
The figure is a diagram for explaining the conventional technology, and Figure 6 is the power supply circuit 1.
FIG. 3 is a waveform diagram of an applied voltage applied to a liquid crystal using a liquid crystal display. 10... Liquid crystal drive circuit, 11... Power supply circuit, 12.
... Frequency divider circuit, 13... Segment drive unit, 14...
- Delay circuit, 15... Common drive section, 16... Concentration control signal generation section, 17-20... Segment drive circuit, 21-24... Common drive circuit, 25... Frequency division circuit, 26... Input circuit, 27... Concentration control pulse generation section, 28A, 28 B, 28 C,... Connection point, 29
,30,43.44.45.58...T-FF,31
．． 32.33.57...Inverter, 34-37.4
1.54-56...NOR circuit, 40-N A N
D Qo road, 42.50-53...EX-OR, 4
6-49...D-FF, 61-66 ・AND circuit, Tri, Tr3, Tr5, Tr7-P type transistor, Tr2, Tr4, Tr6, Tr8
-N-type transistor

Claims (1)

[Scope of Claims] An input section that generates a digital signal corresponding to the display density of a liquid crystal display element, and a pulse generation section that generates a plurality of pulses having mutual delay periods corresponding to the digital signals from the input section. and a common drive unit that generates a common electrode drive signal for the liquid crystal display element, into which the pulse is input and the length of the drive period in the segment electrode drive signal to the liquid crystal display element is changed in accordance with the delay period. A liquid crystal drive circuit comprising a common drive section.