JPS63125471U - - Google Patents

Description

[Brief explanation of the drawing]

Figures 1 to 4 show a PLL as an embodiment of the present invention.
This shows the stabilization circuit. Figure 1 is its electrical circuit diagram, Figure 2 is a block diagram of its preset counter, and Figure 3 is a waveform to explain the operation of the noise removal/horizontal synchronization signal separation circuit. 4 are waveform diagrams for explaining the operation of the PLL phase check circuit, FIGS. 5 to 7 show the conventional PLL error check circuit, and FIG. 6 and 7 are waveform diagrams for explaining the effects, respectively. In the figure, 1...PLL circuit, 1A...phase comparator, 1B...low-pass filter, 1C...VCO (
or VCXO), 1D...1/n frequency divider, 7...Noise removal/horizontal sync signal separation circuit, 8...Composite sync signal line, 9...JK flip-flop, 10...Preset counter, 10A...counter, 10B...flip-flop, 10C...Comparator,
11... Delay element (delay circuit), 12... OR gate, 13... Oscillator, 14... NOT circuit, 15... PL
L phase check circuit, 16... Phase check reference signal generation circuit, 17... Delay element (delay circuit), 18
...D flip-flop as a gate circuit, 18
A...Reset terminal, 19...NOT circuit, 20...Delay element, 21...OR gate, 22...NOT circuit, 2
3, 24... Comparator, 25... Vertical synchronization signal separation circuit, 26... CPU. In addition, in the figure, the same reference numerals are the same,
or a corresponding portion.

Claims (1)

[Scope of utility model registration request] It receives a signal from a composite synchronization signal line that sends a composite signal of horizontal synchronization signals and vertical synchronization signals, removes noise from this composite synchronization signal, and separates the horizontal synchronization signal to perform PLL processing.
A noise removal/horizontal synchronization signal separation circuit that outputs to the circuit, and a PLL phase check circuit that performs a PLL phase check upon receiving the horizontal synchronization signal from the noise removal/horizontal synchronization signal separation circuit and the PLL feedback signal from the PLL circuit. The noise removal/horizontal synchronization signal separation circuit includes a flip-flop which receives a signal from the composite synchronization signal line at its clock input terminal, and receives the output of the flip-flop as a reset release signal and resets it when the required count value is reached. a counter that outputs a signal to the reset terminal of the flip-flop;
It is comprised of a delay circuit that delays the output of the flip-flop, and an OR gate that receives the output of the delay circuit and a signal from the composite synchronization signal line and outputs a horizontal synchronization signal to the PLL circuit, The PLL phase check circuit receives the PLL feedback signal and generates a phase check reference signal having required permissible phase difference information with respect to the PLL feedback signal, and the noise removal/horizontal synchronization signal A delay circuit delays the horizontal synchronizing signal from the separation circuit, receives the phase check reference signal from the phase check reference signal generation circuit, and the delay signal from the delay circuit, and receives the delayed signal within the allowable phase difference. 1. A PLL stabilizing circuit comprising: a gate circuit that outputs an error signal when the PLL stabilizing circuit is not connected.