JPS63124540A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63124540A JPS63124540A JP27116186A JP27116186A JPS63124540A JP S63124540 A JPS63124540 A JP S63124540A JP 27116186 A JP27116186 A JP 27116186A JP 27116186 A JP27116186 A JP 27116186A JP S63124540 A JPS63124540 A JP S63124540A
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- semiconductor chip
- electrode
- metal wire
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000000605 extraction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に表面に電極パッドを有
する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having electrode pads on its surface.
一般に、トランジスタ素子は半導体チップ表面に電極が
形成され、外部引出し用の電極パッドをもっている。特
に、FET構造のものは、入力側の電極パッドと接地側
の電極パッドとが隣接して設けられることが多く、高周
波化が進むと微細化、小型化が進み、上述した2種の電
極パッドの間隔が小さくなり配線用の金属線を接続する
場合、隣の電極パッドに接触しないようにするために接
続の位置精度及び金属線の張り形状について微細な制御
が必要となる。Generally, a transistor element has electrodes formed on the surface of a semiconductor chip, and has electrode pads for external extraction. In particular, in FET structures, the electrode pad on the input side and the electrode pad on the ground side are often provided adjacent to each other, and as the frequency increases, miniaturization and miniaturization progress. When connecting metal wires for wiring as the spacing becomes smaller, fine control is required for the positional accuracy of the connection and the shape of the tension of the metal wires in order to avoid contact with adjacent electrode pads.
第3図(a)及び(b)は従来の半導体装置の一例の平
面図及びB−B’線断面図である。FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along the line BB' of an example of a conventional semiconductor device.
第3図(a)及び(b)に示すよに、第1の電極バット
2と第2の電極バット3は半導体チップ1、上の同一平
面に設けられているなめに、例えば、50μm角の電極
パッド3に直径30μmの金属線6を接続する場合は、
電極パッド2との間・隔を少くとも30μm以上隔てて
おかないと、金属線6が電極バット2に接触することが
ある。As shown in FIGS. 3(a) and 3(b), the first electrode butt 2 and the second electrode butt 3 are provided on the same plane on the semiconductor chip 1. When connecting the metal wire 6 with a diameter of 30 μm to the electrode pad 3,
If the distance between the metal wire 6 and the electrode pad 2 is not kept at least 30 μm, the metal wire 6 may come into contact with the electrode pad 2.
r発明が解決しようとする問題点〕
上述した従来の半導体装置は、隣接した電極パッドの間
隔が小さいトランジスタの場合は、金属線の接続の位置
精度及び張り形状の制御をきわめて微細に行う必要があ
るので、生産性を阻害するという問題点がある。rProblems to be Solved by the Invention] In the conventional semiconductor device described above, in the case of a transistor in which the distance between adjacent electrode pads is small, it is necessary to control the positional accuracy of the connection of the metal wire and the tension shape extremely finely. Therefore, there is a problem that productivity is hindered.
本発明の半導体装置は、半導体チップの表面に設けられ
る第1の電極パッドと、該第1の電極パッドに隣接して
前記第1の電極パッドと段差をもって設けられる第2の
電極パッドとを有している。The semiconductor device of the present invention includes a first electrode pad provided on the surface of a semiconductor chip, and a second electrode pad provided adjacent to the first electrode pad with a step difference from the first electrode pad. are doing.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)及び(b)は本発明の第1の実施例の平面
図及びA−A’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of the first embodiment of the present invention.
第1図(a)及び(b>に示すように、第1の実施例は
トランジスタが形成されている半導体チップ1と、半導
体チップ1の表面に設けられた接地側の第1の電極パッ
ド2と、入力側の第2の電極パッド3と出力側の電極パ
ッド4とを有し、電極パッド2を形成する成分の半導体
チップ1の表面は、例えば、エツチングにより電極パッ
ド3を形成する部分より低く形成されている。As shown in FIGS. 1(a) and (b), the first embodiment includes a semiconductor chip 1 on which a transistor is formed, and a first electrode pad 2 on the ground side provided on the surface of the semiconductor chip 1. , a second electrode pad 3 on the input side and an electrode pad 4 on the output side, and the surface of the semiconductor chip 1 which is the component forming the electrode pad 2 is etched, for example, from the part where the electrode pad 3 is formed. It is formed low.
いま、前述した第3図の従来例の場合と同一条件で電極
パッド3に金属線6を接続するときは、電極パッド2を
電極パッド3より約10μm低くすることにより、両電
極パッド間の平面距離が約10μmになっても金属線6
が電極パッド2に接触することはない。Now, when connecting the metal wire 6 to the electrode pad 3 under the same conditions as in the conventional example shown in FIG. Even if the distance is about 10 μm, the metal wire 6
does not come into contact with the electrode pad 2.
第2図は本発明の第2の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
第2図に示すように、第2の実施例はトランジスタが形
成されている半導体チップ1.と、この半導体チップ1
.の表面に設けられた電極パッド2〜4を有し、電極パ
ッド3を形成する部・分の半導体チップ1.の表面は、
例えば多結晶シリコン層5を形成することにより、電極
パッド2を形成する部分より高く形成している。As shown in FIG. 2, the second embodiment is a semiconductor chip 1. And this semiconductor chip 1
.. The semiconductor chip 1. has electrode pads 2 to 4 provided on the surface of the semiconductor chip 1. The surface of
For example, by forming the polycrystalline silicon layer 5, it is formed higher than the portion where the electrode pad 2 is to be formed.
第2の実施例によれば、例えば、多結晶シリコン層を1
0μm厚に形成することにより、電極パッド2と電極パ
ッド3との平面距離を約10μmにできる。According to the second embodiment, for example, one polycrystalline silicon layer is
By forming the electrode pads to a thickness of 0 μm, the planar distance between the electrode pads 2 and 3 can be approximately 10 μm.
以上説明したように本発明の半導体装置は、第1の電極
パッドとこれに隣接する第2の電極パッドに段差を設け
ることにより、両電極パッドの間隔を小さくしても金属
線で短絡障害を発生することを防止できるので、生産性
を向上できるという効果がある。As explained above, in the semiconductor device of the present invention, by providing a step between the first electrode pad and the second electrode pad adjacent thereto, short-circuit failure due to the metal wire can be avoided even if the distance between the two electrode pads is small. Since this can be prevented from occurring, it has the effect of improving productivity.
第1図(a>及び(b)は本発明の第1の実施例の平面
図及びA−A’線断面図、第2図は本発明の第2の実施
例の断面図、第3図(a)及び(b)は従来の半導体装
置の一例の平面図及びB−B’線断面図である。
1.1.・・・半導体チップ、2.3.4・・・電極パ
ッド、5・・・多結晶シリコン層、6・−・金属線。Figures 1 (a> and (b) are a plan view and a cross-sectional view taken along line A-A' of the first embodiment of the present invention, Figure 2 is a cross-sectional view of the second embodiment of the present invention, and Figure 3 is a cross-sectional view of the second embodiment of the present invention. (a) and (b) are a plan view and a sectional view taken along the line B-B' of an example of a conventional semiconductor device. 1.1. Semiconductor chip, 2.3.4 Electrode pad, 5 ... Polycrystalline silicon layer, 6... Metal wire.
Claims (1)
該第1の電極パッドに隣接して前記第1の電極パッドと
段差をもって設けられる第2の電極パッドとを有するこ
とを特徴とする半導体装置a first electrode pad provided on the surface of the semiconductor chip;
A semiconductor device comprising a second electrode pad provided adjacent to the first electrode pad with a step difference from the first electrode pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27116186A JPS63124540A (en) | 1986-11-14 | 1986-11-14 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27116186A JPS63124540A (en) | 1986-11-14 | 1986-11-14 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63124540A true JPS63124540A (en) | 1988-05-28 |
Family
ID=17496187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27116186A Pending JPS63124540A (en) | 1986-11-14 | 1986-11-14 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63124540A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55143045A (en) * | 1979-04-26 | 1980-11-08 | Mitsubishi Electric Corp | Semiconductor device |
JPS5892258A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Integrated circuit element |
JPS61125044A (en) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-11-14 JP JP27116186A patent/JPS63124540A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55143045A (en) * | 1979-04-26 | 1980-11-08 | Mitsubishi Electric Corp | Semiconductor device |
JPS5892258A (en) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | Integrated circuit element |
JPS61125044A (en) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | Semiconductor device |
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