JPS63124454A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To inhibit leakage currents along the end section of an end section region in an isolation region and the fluctuation of threshold voltage, to increase the surface area of capacitance and to miniaturize a storage cell by forming a capacitance region including the bottom or side surface of a trench shaped to a substrate inside the isolation region while forming a transistor inside the capacitance region. CONSTITUTION:An isolation region 1 surrounds the periphery of a cell, and a capacitance 2 is constituted of an insulating thin-film shaped onto the wall and bottom of a trench and two electrodes of an impurity diffusion layer 7 and poly Si 8. Information from a data line is transmitted over a diffusion layer 7 through a connecting hole 4, and stored in the diffusion layer 7 in the capacitance 2 by opening and closing a PET 3. The surface area of the capacitance 2 is increased by utilizing the wall and the bottom, and one part of the FET 3 is shaped into the trench and an occupying area is reduced. The flow of currents between source-drain in the FET 3 is not made parallel with the end section of the isolation region 1. Consequently, the generation of, leakage currents and the fluctuation of threshold voltage are inhibited. According to the constitution, a small-sized one-transistor storage device is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device consisting of a one-transistor type memory cell, and particularly to its cell structure.

(Prior art)! A transistor type memory cell is one MOS (me
tal oxide semiconductor)
It has a structure in which a transistor and a capacitor (storage capacitance) are connected in series, and there is only one word line and one bit line, making it suitable for high integration. Conventionally, a semiconductor memory device consisting of this type of one-transistor type memory cell has a pattern configuration as shown in FIG. 5, for example. This is a bit line type dynamic RAM (random
In the figure, 1 is a thick insulating film, a deep groove provided on the substrate, or an isolation region formed of the same conductivity type as the substrate and a higher concentration of impurities than the substrate. , each memory cell is electrically isolated by the 11 regions 1. 2 is a capacitor region connected in series with the switching transistor 3; 4 is a contact hole connected to a data line (bit line) 5; and 6 is a word line connected to the transistor 3.

In the above configuration, data transmitted from the data line 5 is transferred to each memory cell via each contact hole 4 connected to the data line 5, and the switching transistor 3 connected to the word line 6 is opened/closed (on/off). OFF), it is stored in the capacitor region 2. At this time, each memory cell is electrically isolated by the isolation region 1 as described above.

[Problem that the invention seeks to solve]

However, in the conventional semiconductor memory device as described above, since the electrode of the switching transistor 3 crosses the isolation region 1, there is a state in which no voltage is applied to the switching transistor 3, that is, a state in which the transistor 3 is off. However, as shown by the arrow in FIG.
There is a problem in that a leakage current flowing along the edge of the capacitor is likely to occur, and data stored in the capacitor region 2 leaks out. Furthermore, since the highly concentrated impurity layer for element isolation is diffused, there is a problem in that the threshold voltage fluctuates.

This invention was made with attention to these problems, and at the same time suppresses the occurrence of leakage current and fluctuations in threshold voltage, and at the same time effectively increases the surface area of the capacitor, thereby reducing the size of the memory cell. The purpose of this invention is to provide a semiconductor memory device with improved performance.

[Means for solving problems]

In the semiconductor memory device of the present invention, an isolation region is provided around the outer periphery of each one-transistor type memory cell, and a storage capacitor region including the bottom or side surface of a groove formed in a substrate is provided inside this isolation region. A transistor is formed inside a storage capacitor region, one electrode of the storage capacitor is connected to one side of an electrode impurity diffusion layer of the transistor, an electrode of the transistor is provided inside the impurity diffusion layer, and the electrode of the transistor is provided inside the impurity diffusion layer. The other side of the impurity diffusion layer is formed inside the electrode, a contact hole connected to a data line is provided in this impurity diffusion layer, and each transistor is connected by a word line.

[Effect]

In this invention, a capacitor region including the bottom or side surface of a trench formed in a substrate is provided inside an isolation region around the outer periphery of a memory cell, and a transistor is further formed inside the capacitor region. In other words, a ring-shaped transistor is formed in the groove, and the channel region and isolation region of this transistor are not arranged in parallel, so the generation of leakage current and fluctuations in threshold voltage are suppressed. , and the surface area of the capacitor is effectively increased.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing the cell structure of a semiconductor memory device according to the present invention. FIG. 1(a) is an example of a basic trench capacitor structure, and FIG. An example of a separate and merged trench capacitor structure at the bottom, part 1 (c) shows different examples of these and separate and capacitor types, respectively.

In FIGS. 1(a), (b), and (C), 1 is an isolation region provided around the outer periphery of each one-transistor type memory cell, and 2 is a capacitor region provided inside this isolation region 1. It is formed to include the bottom or side surfaces of the groove formed in the substrate. 3 is a switching transistor formed inside this capacitor region 2, and one electrode of the capacitor is connected to one side of an impurity diffusion layer 7 for electrode of this transistor. The electrode of the transistor 3 is provided inside the impurity diffusion layer 7, and the other side of the impurity diffusion layer 7 is formed inside this electrode. Further, a contact hole 4 connected to a data line is provided in the central impurity diffusion layer 7, and each transistor 3 is connected by a word line. FIG. 2 is a schematic diagram showing a planar pattern of a semiconductor memory device having the above cell structure.

In FIG. 2(a), the shaded area is the separation region 1,
The solid line inside is the boundary between each memory cell. The method for separating each memory cell, that is, the method for forming the isolation region 1, is as follows.
Methods relying on capacitor structure, known as LOCOS
(local oxidat, ion□f5ilic
There is a method of forming a thick oxide film using the on) method, or a trench isolation method that utilizes trenches provided in the substrate, but in the method shown in Figure 1(a), the isolation region 1 is formed using the LOCO3 method. has been done. However, in either of the isolation methods, an isolation region 1 surrounds each memory cell, and a capacitor region 2 is formed inside this isolation region 1. FIG. 2(b) shows the relationship between the word line 5 and data line 6 in each memory cell, and the contact hole 4 is provided in the center of each cell. Further, FIG. 3 shows an equivalent circuit of each memory cell.

Note that the capacitor region 2 in the memory cell shown in FIG. There is. Further, the capacitor region 2 in the memory cell shown in FIG. 1(b) uses the inner side surface of the trench, and the boundary with other memory cells is at the center of the trench. In the capacitor region 2 of FIG. 1(C), one electrode 8 is connected to the diffusion layer 7 of the transistor 3, and this electrode, a thin insulating film formed on its surface, and a thin insulating film formed on its entire surface are connected to the diffusion layer 7 of the transistor 3. and another electrode 9.

In the semiconductor memory device configured as described above, data from the data line 6 is transmitted through the contact hole 4 to the impurity diffusion layer 7, which is the source/drain electrode of the switching transistor 3, and by opening and closing the transistor 3, the data is transmitted to the impurity diffusion layer 7, which is the source/drain electrode of the switching transistor 3. is stored in the impurity diffusion layer 7. Here, since the capacitor region 2 has a structure including the side or bottom surface of the groove provided in the substrate, or both surfaces thereof, the capacitor surface area can be effectively increased. Furthermore, the switching transistor 3 is formed so that a part or all of it fits into the above-mentioned groove. FIG. 1(a) shows an example in which a part of the transistor 3 is formed in the groove, and FIG. 1(b) shows an example in which the entire transistor 3 is formed in the groove. Therefore, the area occupied by the switching transistor 3 can be reduced, which also facilitates reduction in the area of the memory cell.

Further, the switching transistor 3 has a lower side (
The bottom side of the trench) is surrounded by a diffusion layer (source or drain) connected to one electrode of the capacitor region 2, and the inside (above it if it is in the trench) is surrounded by a diffusion layer (drain or source) connected to the data line 6. ) with MO3I
- A transistor, which is arranged so that the channel region of this MOS transistor 3, that is, the current flow in the current path between the source and the train, is not parallel to the end of the isolation region 1. That is, since the switching transistor 3 has a ring shape within one cell, the flow of electrons from the source to the drain is not parallel to the edge of the isolation region 1 at all. At this time, the groove forming the capacitor region 2 also has a ring shape.

One contact hole 4 connected to the data line 6 is formed in the diffusion layer 7 inside the switching transistor 3. Further, the switching transistor 3 of each memory cell is connected to the word line 5, and the connection may be made in the same layer as the transistor 3, or may be connected in another layer, such as an aluminum line. In the latter case, it is necessary to form a contact hole 4 with the word line 5 in a part of each switching transistor 3.

Next, when arranging word lines 5 and data lines 6 after forming each memory cell, in the case of the folded pit line method, two types of data lines 6 with inverted signals are arranged alternately, so that When each contact hole 4 is placed on one word line 5, two memory cells are selected at the same time, so that one of them must be placed under the next word line 5. Therefore, Fig. 2(b)
As shown in the figure, the cells are arranged in a houndstooth pattern.

The shape of this memory cell may be circular or dogleg-shaped, but by making it hexagonal as shown in Figure 4, the area can be used effectively, and it has acute angles that tend to cause electric field concentration. It can be said that it is an ideal form because it is not. in this case,
It is desirable that the contact hole 4 is placed in the center of the memory cell, and the distance "x + b x r CX" to each side is the same as the target distance a V + b V + C3/.

The distances aX, bX, and cX on each side vary depending on how the pitches of the word lines 5 and data lines 6 are selected; in the case of the folded pit line method, each cell has 1.5 data lines 6. Since one word line 5 is required, the pitch needs to be wider than when one word line 5 is required. Therefore, a cell shape is required such that the distance between each side is a,<b=C. However, in the case of the oven bit line method, the cells need only be arranged vertically and horizontally in regular rows, so there is no need for hexagonal arrangement.

As described above, this embodiment has a pattern in which each memory cell has one contact hole 4 connected to the data line 6 in the center, the switching transistor 3 is arranged around the contact hole 4, and the isolation region 1 is further arranged outside the contact hole 4. It has become. Therefore, current flow in the channel region of the switching transistor 3 is not parallel to the edge of the isolation region 1, suppressing the occurrence of leakage current, and diffusion of the impurity diffusion layer 7 from the edge of the isolation region 1. Fluctuations in the threshold voltage caused by this are also suppressed, and stable characteristics of the transistor 3 can be obtained. In addition, by arranging each memory cell in a hexagonal pattern in a staggered pattern as described above, it can also be applied to the folded pit line method, and leakage between cells due to electric field concentration at the cell edges can be avoided. It can be suppressed. Furthermore, by forming part or all of the capacitor region 2 and the switching transistor 3 into a trench structure, it is possible to increase the capacitance of the capacitor and to reduce the size of the memory cell.

Note that the present invention is applicable not only to dynamic RAM but also to all other memory devices consisting of one transistor and one capacitor type memory cell.

〔Effect of the invention〕

As explained above, according to the present invention, an isolation region is provided around the outer periphery of each one-transistor type memory cell, and a capacitor region including the bottom or side surface of the groove formed in the substrate is provided inside the isolation region. At the same time, since the transistor is formed inside this capacitor region, it is possible to suppress the occurrence of leakage current flowing along the edge of the isolation region of the transistor and the fluctuation of the threshold voltage, and also to reduce the effective surface area of the capacitor. This has the effect of increasing the size of the memory cell and reducing the size of the memory cell.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (c) are cross-sectional views showing the cell structure of a semiconductor memory device according to the present invention, and FIG.
), (b) is a plan pattern diagram of a semiconductor memory device having the cell structure shown in FIG. 1, FIG. 3 is an equivalent circuit diagram of the memory cell shown in FIG. 2, and FIG. 4 is a shape of the memory cell shown in FIG. 2. FIG. 5 is a plan pattern diagram showing a conventional example. 1--------Separation region 2-----Capacitor region 3--Switching transistor 4--------
Contact hole 5 --- Word line 6 --- Data line 7 --- Impurity diffusion layer Note that the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] In a semiconductor memory device consisting of a one-transistor type memory cell, an isolation region is provided around the outer periphery of each memory cell, and a storage capacitor region is provided inside the isolation region including the bottom or side surface of a groove formed in a substrate, and forming a transistor inside the storage capacitor region, connecting one electrode of the storage capacitor to one side of an electrode impurity diffusion layer of the transistor, and providing an electrode of the transistor inside the impurity diffusion layer; A semiconductor memory device characterized in that the other side of the impurity diffusion layer is formed inside this electrode, a contact hole connected to a data line is provided in this impurity diffusion layer, and each transistor is connected by a word line.