JPS63124163A - Processor array - Google Patents

Abstract

PURPOSE:To process complicated arithmetic operations having many variables at a high speed without increasing the number of input/output pins of each processor element and computing elements, by using a timing generating circuit and plural processor elements. CONSTITUTION:A timing signal of T0 is outputted to each processor element 2 from a timing generating circuit 1 in accordance with a synchronizing signal SYNC. While an element PE1 reads the input data for t0 and outputs it to the following element PE2 after arithmetic. Then a timing signal of T1 is outputted from the circuit 1 and the element PE1 outputs the input data for T1 to the PE2 after arithmetic. The PE2 outputs the input received from the PE1 to an element PE3 after arithmetic. Thus a timing signal of T2 is processed in the same way and a single piece of data is inputted to the PE1 for a period of T0-T2 and calculated by each element 2 with each delay equivalent to a single timing in terms of a pipeline. Then the results of arithmetic are successively outputted from an element PE12 set at the right edge. In such a way, the complicated arithmetic operations are carried out at a high speed while each element 2 is calculated in time division with a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a processor array having a one-dimensional array structure in the information processing field.

BACKGROUND ART A conventional processor array is a systolic array proposed by H. T. Kung of Carnegie Mellon University in the United States (for example, C. Mead, L.
"Introduction to Ultra LSI Systems" (June 30, 1981), co-authored by Conway, translated and supervised by Takuo Kanno and Hiroyuki Sakaki.

Baifukan, P299-P318) 0 Figure 3 shows an example of this conventional processor array, where a is a multiplication formula for a band matrix with a band width of 4 and a vector, and b is a one-dimensional array that performs the multiplication. 4 connected in a shape
3 is a configuration diagram of a processor array including processor elements 3. FIG.

The operation of the conventional processor array configured as described above will be described below.

Each processor element has three registers RA.

It has Rx and Ra, and holds the contents of band matrix A, vector I, and vector y, respectively. Initially, the values of all registers are 0. Within each processor element,
First, a new element in the band of matrix A is placed in register RA, and register R of the processor element on the left is placed in register R8.
1, and the contents of register R of the processor element on the right are taken into register R. Next, R a+RA x
R! performs the calculation and stores the result in register nA. In this way, A moves downward, X moves to the right, and y moves to the left among the processor elements, and the product y of the banded matrix and vector is sequentially output from the leftmost processor element as shown in Figure 4. go.

Problems to be Solved by the Invention However, in the above configuration, the type of input/output data in each cycle and the content of the calculation within the processor element are the same, so the processor element In view of these problems, the present invention has the problem of requiring a small number of input/output bins and a calculation unit in the processor element, even when there are many types of data to be calculated. It is an object of the present invention to provide a processor array that can be configured using processor elements consisting of arithmetic units.

Means for Solving the Problems The present invention provides a method for converting a timing signal (τ.~T
m), and the position of To of the timing signal can be set by a synchronization signal, and a timing generation circuit that reads the same type of input data from the previous stage with a delay of one timing compared to the previous stage, and performs different arithmetic processing at each timing. This is a processor array comprising n processor elements connected in cascade in one-dimensional unidirectional direction.

Effect: With the above-described configuration, the present invention can read different types of data at different timings and perform different arithmetic processing within each processor element, without increasing the number of input/output bins and the number of arithmetic units of each processor element. , complex processing with many variables can be performed at high speed.

Embodiment FIG. 1 shows a configuration diagram of a processor array in the case of m=2°n;12 in an embodiment of the present invention. In FIG. 1, 1 is T0 to T according to the input clock CLK.
2 is a timing generation circuit that can generate the timing signal No. 2 and set the position of the timing signal To by the synchronization signal 5YNC; and No. 2 is a processor element that performs different arithmetic processing depending on the internal timings 70 to T2.

The operation of the processor array of this embodiment configured as described above will be described below.

First, a timing signal To is generated from the timing generation circuit 1 in accordance with the synchronization signal 5YNC, and is output to each processor element 2. Each processor element 2
Since there is a delay of one timing between receiving input data and outputting the calculation result, the internal timing signal is also connected so as to be delayed by one timing. Therefore, as shown in FIG. 2, when the timing signal To is generated from the timing generation circuit 1, the first processor element PE reads the input data for t0 and performs the calculation for 70 at t1! After that, it is output to the next stage processor element PE2. Next, when the timing signal T1 is generated from the timing generation circuit 1, P
E reads the input data for sac, and performs the calculation for t, and then outputs the calculation result to PE2, and PE2 calculates t.

The result of the calculation is input, the calculation for t0 is performed, and the result is output to PE3. Furthermore, when the timing signal T3 is generated from the timing generation circuit 1, PE calculates the data of t, PE2 calculates the data of t, and PE3 calculates the data of t.
Then, the data of to is calculated. Like this T0~T2
During this period, one piece of data is input to PE1, and as shown in FIG.
The calculation results are sequentially output from 2 onwards.

As described above, according to this embodiment, by connecting the timing signals generated from the timing generation circuit to each processor element with a shift of one, each processor element can be connected in a time-sharing manner with a simple system configuration. Complex processing with many variables can be performed while performing calculations.

In this embodiment, it is assumed that the calculation result is obtained from the rightmost processor element PE,2, but a register for storing the result is provided in each processor element, and the configuration is such that the result is output from each processor element through a global output bus. As described in detail, according to the present invention, complex processing with many variables can be performed at high speed without increasing the number of input/output bins and the number of arithmetic units of each processor element. It can be done, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a grosser array according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the same embodiment, and FIG. 3 is a configuration diagram of a conventional grosser array and how to solve the problem using the grosser array. FIG. 4 is an explanatory diagram of the operation of the conventional example. 01...--timing generation circuit, 2...-processor element. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure PEf PE? PEJPE4 Ka 3 (ku)

Claims (1)

[Claims] A timing generation circuit that generates a timing signal (T_o to T_m) from an input clock and can set the position of T_o of the timing signal using a synchronization signal, and 1.
A processor array comprising n processor elements cascaded in a one-dimensional unidirectional direction that read input data of the same type from a previous stage with a timing delay, perform different arithmetic processing at each timing, and output it to the next stage.