JPS63122096A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speed up an access by providing a charge means at a side opposite to the row decoder of row lines, and charging up a row line speedily if the line is selected. CONSTITUTION:When address data A1-An shift and a row line is selected, a control signal phi temporarily goes to a high level, and the potential at a point C goes to a ground potential VS. Thereafter, if the row line is charged up, the potential of the point A reaches a high voltage level comparatively fast, but that of a point B rises only gradually because of the resistor and the stray capacity of the row line. When the potential of the point C exceeds the logical threshold of an inverter circuit 3 through a capacity element C1, the output of the circuit 3 goes to a low level, a P-type MOSFET Tr4 turns on to supply a high voltage from the power source VC to the point B. Therefore, the charge-up of a selected row line is quickly executed, hence the access is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor memory device, and more particularly to a large-capacity semiconductor memory device with reduced wiring delay time.

<Prior Art> Semiconductor storage devices include, for example, nonvolatile semiconductor memories whose memory elements are MO3 field effect transistors (hereinafter referred to as MO8FETs) having a two-layer gate structure of a floating gate and a control gate.

FIG. 4 shows a cross-sectional view of this memory element, and FIG. 5 shows its symbol.
N0-type source/drain diffusion layers 12 and 13 are provided on the substrate 1, and a floating gate 14 electrically insulated from the outside by an insulating layer on the substrate, and a control gate 15 for controlling switching of the memory element. is provided. When the floating gate of this memory element is electrically neutral,
It becomes conductive at a low control gate voltage (e.g. 2V), but when a high voltage (e.g. 20V) is applied to the control gate and drain, electrons are injected into the floating gate and the threshold voltage of the memory element as seen from the control gate increases. becomes high and becomes conductive unless a high voltage (for example, 8V) is applied to the control gate. That is, as shown in FIG. 6, when the floating gate is in an electrically neutral state, the memory element becomes conductive at a low control gate voltage as shown by the solid line 16, but when electrons are injected into the floating gate, the memory element becomes conductive as shown by the solid line 17. As shown in FIG. Able to memorize information. FIG. 7 is a plan view of a memory array actually constructed using the above-mentioned memory elements. That is, it is provided with a plurality of row lines WL, W, W3, .
, M C13""" are arranged. In this case, the opposing memory elements Me11 and M Q zx s M Q x
*, MQ 22, and so on have their drain electrodes set opposite to each other and commonly connected to the column line, and their sources are connected to the ground potential GND. In the memory array above,
Polycrystalline silicon (hereinafter referred to as polysilicon) in which impurities are diffused at a high concentration is generally used as the wiring material for the row lines.

The resistance value is relatively high, for example, the sheet resistivity is ρ5=20
Ω/mouth.

<Problems to be Solved by the Invention> In a large-capacity semiconductor storage device equipped with such a memory array, the increase in the number of memory elements increases the length of the row line wiring, and the wiring width is also narrow, so the row line The resistance distributed in the row lines is large, and the parasitic capacitance distributed in the row lines is also large, and the wiring delay due to the resistance and capacitance distributed in the row lines deteriorates the data read speed. For example, as shown in FIG. 8, row lines with a wiring length of 1500 μm and a wiring width of 1.5 μm are formed of polysilicon with a sheet resistivity ρ5=20Ω/hole to form memory elements Mc4, M844, . . . Mc4n. It is assumed that a control gate is used and a row decoder 20 is connected to one end of this row line. First, the resistance Rw of the row line at this time is calculated by the following formula (
As shown in 1), Rw=ρsxLw/Ww...Equation (1) where ρ
S: Sheet resistivity of wiring material (Ω/hole) Lw: Wiring length of row line Ww: Wiring width of row line where p s = 20%, Lw = 1500 μm, Ww
By substituting ='1.5 μm, Ω is obtained in Rw=20.

Furthermore, the wiring delay will be considered assuming that the wiring capacitance parasitic to this row line is Cw=3 pF. Now, for the sake of simplicity, the circuit shown in FIG. 8 is changed to a series circuit of a row line resistance Rw' and a capacitance Cw' as shown in FIG. 9, and a voltage source v is used as a row decoder.
Give 0. Here, the farthest point from the row decoder on the row line
corresponds to X', but if the voltage at time 1=0 at point X' is Vx'(0)=O, then point X at time t
As is well known, the voltage Vx' (t) at ' is calculated as shown in equation (2).

Vx'(t) ==VO(1-e-pzw-cw')
-Equation (2) Solving this equation (2) for t gives the following equation (3)
become that way.

t= -Rw'・Cw' ・1 n(1-V'X(t
)/Vo)...Formula (3) Here, assuming that the voltage source V is 5V, and finding the time t (X' = 4V) required for the point X' to become 4V, t (X'
=4V)=-20000X3X10-”Xln (1
-415) =96.6X10-'sec...Equation (4) In other words, 96°6N until point X' becomes 4v from Ov
sec is required. In this way, in a large-capacity semiconductor memory device, the wiring delay of the row line is large and the voltage rise at a point far from the row decoder on the row line selected by the single row decoder is very slow, so the memory element There was a problem that it was difficult to establish a conductive state and the data read speed was slow.

In addition, in order to reduce the wiring delay of the 5-row line, it is possible to provide multiple row decoders and subdivide the row lines, but subdividing the row lines requires adding more row decoders, which reduces the chip size of the semiconductor memory device. Since the size is increased, a problem arises in that the manufacturing yield is reduced.

Therefore, the present invention does not require adding a row decoder,
It is an object of the present invention to provide a semiconductor memory device that can reduce wiring delay time.

<Means, operations, and effects for solving the problems> The present invention includes a memory cell array in which a plurality of memory elements are arranged in a matrix, and a row line corresponding to the address data is selected from a plurality of row lines based on the address data. and a row decoder for shifting the selected row line to a predetermined potential to activate memory elements commonly connected to the row line, wherein charging means is connected to the row line near the memory element. However, it is characterized in that only the row line selected by the row decoder among the plurality of row lines is rapidly brought to the predetermined potential by the charging means. Therefore, in the semiconductor memory device according to the present invention, 1
When a specific row line is selected by the row decoder, the selected row line is brought to a predetermined potential by the row decoder and charging means, thereby activating the memory element.

In this way, the row line potential is controlled by the row decoder and the charging means, so even if the row line is made finer to increase the storage capacity, the speed of change in the row line potential does not decrease, and the memory element can be used at high speed. This has the effect of being able to access. Moreover, the number of row decoders does not increase as when dividing row lines, so
There is no significant increase in chip size and, therefore, no reduction in manufacturing yield.

<Example> Next, a first embodiment of the present invention will be described with reference to the drawings.

The first embodiment shown in FIG.
A case is shown in which this is realized using an OS transistor (hereinafter referred to as CMO8).

A row decoder circuit that predecodes address data A1, A2, . . The row line operates as a common control gate for a plurality of memory elements Mc, Mc, . . . Mc m. Also.

One end A of the row line connected to the row decoder and the opposite end B are connected to a P-type MOSFET Tr via a capacitive element C1.
, and an N-type MOSFET Tr=.

N-type MO8FET Tr1 as the second transistor
Its drain is connected to the connection point C between the capacitive element C0 and the inverter circuit 3, its source is connected to the ground potential Vs, and its gate is connected to a control signal that is at a high level for a predetermined period of time from the time of address data change. A signal Φ is provided. P-type MOSFET Tr as the first transistor
The source of 4 is connected to the voltage source Vc, the drain thereof is connected to one end B of the row line, and the gate thereof is connected to the output of the inverter circuit 3. The above inverter circuit 3 and MO
The SFETs Tro and Tr4 and the capacitive element C□ collectively constitute charging means.

Next, the operation of the circuit shown in FIG. 1 will be explained. Third
The figure is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 1. First, when the address data changes and the row line shown in FIG. 1 is selected (Ta), the control signal Φ temporarily becomes high level, and the potential at point C becomes equal to the ground potential Vs. Further, the row decoder operates to charge up the row line. However, although the potential at point A reaches a high voltage relatively quickly, the resistance Rw and capacitance C distributed on the row lines
Due to w, the potential at point B does not rise rapidly, but as the potential at point B rises, the potential at point C rises via capacitive element C, and this potential at point C increases the potential of inverter circuit 3. When the logic threshold is exceeded, the output of the inverter circuit 3 becomes low level, and as a result, the P-type MOSFET T
Since r becomes conductive, a high voltage is supplied from the voltage source Vc, and the potential at point B rapidly rises. Next, when the address data changes and the above row line becomes unselected (T
In b), first, the control signal Φ temporarily becomes high level, so that the potential at one point C becomes equal to the ground potential VS, the output of the inverter circuit 3 becomes high level, and the P-type M
Since the OSFET becomes non-conductive, the potential of the first row line is lowered to the ground potential Vs by the row decoder.

Next, how much speedup can actually be achieved by providing the charge-up circuit will be explained. First, in FIG. 1, the capacitance of the capacitive element C1 is C1=O.

2 pF, the parasitic capacitance at point C is Cc = 0.05 pF, the voltage at point B at time 0 is VB (t), the voltage at point C is VC (t), and at time 1 = 0 VB (0 )=
When VC(0)=O and MOSFET Trl is in a non-conducting state, VB(t) and VC(
t) as shown in the following equation (5).

V C (t) = (Cx X V B (t))
/ (C1+Cc)=0.8VB (t) −
--Equation (5), where the logic threshold of the inverter circuit 3 is 1v, and the above equation (5) is expressed as VC(t')=
Determining VB (t') as tv, VB (t') = 110.8 = 1.25V In other words, when the potential at point B becomes 1.25V, the output of the inverter circuit 3 is inverted and becomes Low, MOSFE
T Tr4 becomes conductive. moreover.

As in the example of FIG. 9, the resistance of the row line Rw' = 20 and the Ω capacitance Cw' = 3pF, the time t required for the potential of one point B to reach 1.25V (B = 1.25V) is: From the above formula (3), t (B=1.25V)=-20000X3XIO-"
Xln (1-1,2515)=17.3X10-'s
It becomes ec. For the sake of simplicity, if we evaluate the wiring delay using an RC time constant, the conventional semiconductor memory device explained in Fig. 8 requires Rw'XCw' = 6 ON sec, but the By providing the charge-up circuit of the embodiment, 17.3 Nsec is required until the charge-up circuit operates, and from the time the charge-up circuit operates, the row line is charged from both ends of point A and point B on the row line. As a result, the RC time constant becomes 1/2Rw'Xi/2Cw'=15Nsec.

The tenor time t (B = 1.25V) = 17.3N until the charge-up circuit operates with this 15Nsec
The total speed is 32.3Nsec, which is about twice the speed. FIG. 2 is a circuit diagram showing a second embodiment in which the present invention is implemented using complementary MO8. 0 row decoders XD1, XD, .
Wo,...W, are connected to one end, and this row line W2 is connected to W.
The other end to which the row decoder is not connected to 22,...W, is an N-type MOSFET T'r*x, Tr22.
, ... are commonly connected via Tr2k, and this commonly connected point B' is connected to a P-type MO8F via a capacitive element C2.
ETTr, and an N-type MOSFET Trl.

The drain of the N-type MOSFET Trll is connected to the connection point C' between the capacitive element C2 and the inverter circuit 32, the source is connected to the ground potential Vs, and the gate is connected to the high level for a predetermined period of time after the address data changes. A control signal Φ' is supplied. P-type MOSFET Tr
The source of 14 is connected to the voltage source Vc, the drain is connected to the point B', and the gate is connected to the output D' of the inverter circuit. N-type MOS FET T r, □, T
r2. ,...The gate of Tr2 has row lines WaX, W
22... A decoding circuit CX that generates signals aci, ac, . . . ack for selecting one of W2.
The outputs of D are respectively supplied. In this second embodiment,
Its operation is almost the same as that of the first embodiment shown in FIG.
Type MOSFET Tr, □, Tr,...Tr
2k to the charge-up circuit, and furthermore, these N-type MOSFETs Tr21, Trtz,...
Decode signal ac is applied to the gate of Tr2, ac2,...
By connecting and decoding ack, it is only necessary to provide one charge-up circuit for each row line. Therefore, it is necessary to provide a charge-up circuit more than the first embodiment of the present invention shown in FIG. This has the advantage that the increase in chip size of the semiconductor memory device due to this can be suppressed to a low level.

As explained above, in each of the above embodiments, an inverter circuit is provided, the input of the inverter circuit is connected to the row line via the inverter, and the first MO having the first conductivity type is connected to the row line.
The gate of the SFET is connected to the output of the inverter circuit, its source to the first voltage source, and its drain to the row line, and the drain of a second MOSFET having a second conductivity type is connected to the inverter circuit. The source is connected to a second voltage source at the connection point between the input of the inverter circuit and the capacitive element, and when the address data changes, the connection point between the input of the inverter circuit and the capacitive element is connected to the second voltage source for a predetermined period of time. Since we have provided a charge-up circuit whose gate is connected to a control signal that has the same potential as the voltage source, when the voltage of the row line selected by the row decoder increases, the charge-up circuit operates and rapidly increases the voltage. can be done.

As a result, even if miniaturization is attempted to increase storage capacity, there is no delay in signal wiring propagation, and data can be read out at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a first embodiment of the present invention, FIG. 2 is a block circuit diagram showing a second embodiment of the present invention, and FIG.
The figure is a waveform diagram of main nodes explaining the operation of the first embodiment,
FIG. 4 is a cross-sectional view showing the structure of the memory element, FIG. 5 is a symbol diagram showing equivalent symbols of the memory element, FIG. 6 is a graph explaining the function of the memory element, and FIG. 7 is a plan view of the memory cell array. FIG. 8 is a block circuit diagram showing a conventional example,
FIG. 9 is an equivalent circuit diagram of a conventional example. Mc, Mc...M a m...Memory element. XD engineering, XD,...XDk...row decoder, W
21. Wo,...W2k...row line, 1...
・・・・・・Pre-decoder, 3.32・・・・・・
...Inverter circuit, V Cr V s...
...Voltage source, T rl t T r 11...
...Second transistor, Tr,,Tr,4...First transistor. \\-I/ Figure 4% Figure 7 Figure 8 X' Figure 9

Claims (2)

[Claims] (1) A memory cell array in which a plurality of memory elements are arranged in a matrix, a row line corresponding to the address data is selected from a plurality of row lines based on address data, and the selected row line is shifted to a predetermined potential. In a semiconductor memory device having a row decoder that activates memory elements commonly connected to the row line, a charging means is connected to the row line near the memory element, and the row decoder selects one of the plurality of row lines. 1. A semiconductor memory device characterized in that only the row lines that have been charged are rapidly brought to the predetermined potential by the charging means. (2) The charging means is disposed between an inverter circuit whose input is connected to a row line via a capacitive element and inverts when the row line is selected, the first voltage source, and the row line. A first transistor that connects the first voltage source and the row line to transfer the row line to the predetermined voltage when the inverter circuit is inverted, and a voltage different from the first voltage source can be supplied. is arranged between a second voltage source and an input of the inverter circuit, and when the row line is not selected, conducts the second voltage source and the input of the inverter circuit to forcibly operate the inverter circuit. 2. The semiconductor memory device according to claim 1, further comprising a second transistor that is brought into a non-inverted state.